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-rw-r--r--backends/firrtl/firrtl.cc3
-rw-r--r--backends/jny/jny.cc5
-rw-r--r--backends/json/json.cc5
-rw-r--r--backends/rtlil/rtlil_backend.cc5
-rw-r--r--frontends/ast/ast.cc3
-rw-r--r--frontends/ast/simplify.cc3
-rw-r--r--frontends/verific/verific.cc10
-rw-r--r--frontends/verific/verificsva.cc4
-rw-r--r--kernel/fstdata.cc2
-rw-r--r--kernel/register.cc7
-rw-r--r--kernel/yosys.cc4
-rw-r--r--passes/cmds/bugpoint.cc1
-rw-r--r--passes/cmds/design.cc5
-rw-r--r--passes/opt/opt_ffinv.cc3
-rw-r--r--passes/proc/proc_dff.cc2
15 files changed, 39 insertions, 23 deletions
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index e483117d1..d68c52563 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -1238,6 +1238,9 @@ struct FirrtlBackend : public Backend {
if (top == nullptr)
top = last;
+ if (!top)
+ log_cmd_error("There is no top module in this design!\n");
+
std::string circuitFileinfo = getFileinfo(top);
*f << stringf("circuit %s: %s\n", make_id(top->name), circuitFileinfo.c_str());
diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc
index 2b8d51b76..0be11a52c 100644
--- a/backends/jny/jny.cc
+++ b/backends/jny/jny.cc
@@ -546,8 +546,9 @@ struct JnyPass : public Pass {
std::ostream *f;
std::stringstream buf;
+ bool empty = filename.empty();
- if (!filename.empty()) {
+ if (!empty) {
rewrite_filename(filename);
std::ofstream *ff = new std::ofstream;
ff->open(filename.c_str(), std::ofstream::trunc);
@@ -565,7 +566,7 @@ struct JnyPass : public Pass {
JnyWriter jny_writer(*f, false, connections, attributes, properties);
jny_writer.write_metadata(design, 0, invk.str());
- if (!filename.empty()) {
+ if (!empty) {
delete f;
} else {
log("%s", buf.str().c_str());
diff --git a/backends/json/json.cc b/backends/json/json.cc
index 1ff0a6c66..fd2c922fd 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -666,8 +666,9 @@ struct JsonPass : public Pass {
std::ostream *f;
std::stringstream buf;
+ bool empty = filename.empty();
- if (!filename.empty()) {
+ if (!empty) {
rewrite_filename(filename);
std::ofstream *ff = new std::ofstream;
ff->open(filename.c_str(), std::ofstream::trunc);
@@ -683,7 +684,7 @@ struct JsonPass : public Pass {
JsonWriter json_writer(*f, true, aig_mode, compat_int_mode);
json_writer.write_design(design);
- if (!filename.empty()) {
+ if (!empty) {
delete f;
} else {
log("%s", buf.str().c_str());
diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc
index b5163aefe..7c7e26a93 100644
--- a/backends/rtlil/rtlil_backend.cc
+++ b/backends/rtlil/rtlil_backend.cc
@@ -530,8 +530,9 @@ struct DumpPass : public Pass {
std::ostream *f;
std::stringstream buf;
+ bool empty = filename.empty();
- if (!filename.empty()) {
+ if (!empty) {
rewrite_filename(filename);
std::ofstream *ff = new std::ofstream;
ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc);
@@ -546,7 +547,7 @@ struct DumpPass : public Pass {
RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n);
- if (!filename.empty()) {
+ if (!empty) {
delete f;
} else {
log("%s", buf.str().c_str());
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 6097f02f5..982943d1b 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1649,7 +1649,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
AstNode *new_ast = NULL;
std::string modname = derive_common(design, parameters, &new_ast, quiet);
- if (!design->has(modname)) {
+ if (!design->has(modname) && new_ast) {
new_ast->str = modname;
process_module(design, new_ast, false, NULL, quiet);
design->module(modname)->check();
@@ -1699,6 +1699,7 @@ std::string AST::derived_module_name(std::string stripped_name, const std::vecto
std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet)
{
std::string stripped_name = name.str();
+ (*new_ast_out) = nullptr;
if (stripped_name.compare(0, 9, "$abstract") == 0)
stripped_name = stripped_name.substr(9);
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index da7933d2f..71a26983b 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -4705,8 +4705,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
children_flags |= AstNode::MEM2REG_FL_ASYNC;
proc_flags_p = new dict<AstNode*, uint32_t>;
}
-
- if (type == AST_INITIAL) {
+ else if (type == AST_INITIAL) {
children_flags |= AstNode::MEM2REG_FL_INIT;
proc_flags_p = new dict<AstNode*, uint32_t>;
}
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index a93d79c80..8898c4597 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2317,8 +2317,8 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
}
- veri_module = (lib && module_name) ? lib->GetModule(module_name->GetName(), 1) : 0;
- top = veri_module->GetName();
+ if (lib && module_name)
+ top = lib->GetModule(module_name->GetName(), 1)->GetName();
}
}
@@ -2344,6 +2344,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
int i;
FOREACH_ARRAY_ITEM(netlists, i, nl) {
+ if (!nl) continue;
if (!top.empty() && nl->CellBaseName() != top)
continue;
nl->AddAtt(new Att(" \\top", NULL));
@@ -3297,8 +3298,8 @@ struct VerificPass : public Pass {
const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
}
- veri_module = (lib && module_name) ? lib->GetModule(module_name->GetName(), 1) : 0;
- top_mod_names.insert(veri_module->GetName());
+ if (lib && module_name)
+ top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName());
}
} else {
log("Adding Verilog module '%s' to elaboration queue.\n", name);
@@ -3333,6 +3334,7 @@ struct VerificPass : public Pass {
int i;
FOREACH_ARRAY_ITEM(netlists, i, nl) {
+ if (!nl) continue;
if (!top_mod_names.count(nl->CellBaseName()))
continue;
nl->AddAtt(new Att(" \\top", NULL));
diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index 12bac2a3d..986a98643 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -1777,7 +1777,7 @@ struct VerificSvaImporter
if (mode_assert) c = module->addLive(root_name, sig_a_q, sig_en_q);
if (mode_assume) c = module->addFair(root_name, sig_a_q, sig_en_q);
- importer->import_attributes(c->attributes, root);
+ if (c) importer->import_attributes(c->attributes, root);
return;
}
@@ -1822,7 +1822,7 @@ struct VerificSvaImporter
if (mode_assume) c = module->addAssume(root_name, sig_a_q, sig_en_q);
if (mode_cover) c = module->addCover(root_name, sig_a_q, sig_en_q);
- importer->import_attributes(c->attributes, root);
+ if (c) importer->import_attributes(c->attributes, root);
}
}
catch (ParserErrorException)
diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc
index 1b8043f9a..65ae3426c 100644
--- a/kernel/fstdata.cc
+++ b/kernel/fstdata.cc
@@ -197,7 +197,7 @@ static void reconstruct_clb_attimes(void *user_data, uint64_t pnt_time, fstHandl
void FstData::reconstruct_callback_attimes(uint64_t pnt_time, fstHandle pnt_facidx, const unsigned char *pnt_value, uint32_t /* plen */)
{
- if (pnt_time > end_time) return;
+ if (pnt_time > end_time || !pnt_value) return;
// if we are past the timestamp
bool is_clock = false;
if (!all_samples) {
diff --git a/kernel/register.cc b/kernel/register.cc
index 0e4d503be..9ffb17c1a 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -531,10 +531,11 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
std::ifstream *ff = new std::ifstream;
ff->open(filename.c_str(), bin_input ? std::ifstream::binary : std::ifstream::in);
yosys_input_files.insert(filename);
- if (ff->fail())
+ if (ff->fail()) {
delete ff;
- else
- f = ff;
+ ff = nullptr;
+ }
+ f = ff;
if (f != NULL) {
// Check for gzip magic
unsigned char magic[3];
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 333faae6a..bd8dded4b 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -469,8 +469,8 @@ std::string make_temp_dir(std::string template_str)
# endif
char *p = strdup(template_str.c_str());
- p = mkdtemp(p);
- log_assert(p != NULL);
+ char *res = mkdtemp(p);
+ log_assert(res != NULL);
template_str = p;
free(p);
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
index e666023fa..c398afffa 100644
--- a/passes/cmds/bugpoint.cc
+++ b/passes/cmds/bugpoint.cc
@@ -393,6 +393,7 @@ struct BugpointPass : public Pass {
}
}
}
+ delete design_copy;
return nullptr;
}
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 169f7cc4a..168d38563 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -118,6 +118,9 @@ struct DesignPass : public Pass {
std::string save_name, load_name, as_name, delete_name;
std::vector<RTLIL::Module*> copy_src_modules;
+ if (!design)
+ log_cmd_error("No default design.\n");
+
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
@@ -280,7 +283,7 @@ struct DesignPass : public Pass {
done[mod->name] = prefix;
}
- while (!queue.empty())
+ while (!queue.empty() && copy_from_design)
{
pool<Module*> old_queue;
old_queue.swap(queue);
diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc
index 5d989dafd..3f7b4bc4a 100644
--- a/passes/opt/opt_ffinv.cc
+++ b/passes/opt/opt_ffinv.cc
@@ -64,6 +64,7 @@ struct OptFfInvWorker
log_assert(d_inv == nullptr);
d_inv = port.cell;
}
+ if (!d_inv) return false;
if (index.query_is_output(ff.sig_q))
return false;
@@ -140,6 +141,7 @@ struct OptFfInvWorker
log_assert(d_lut == nullptr);
d_lut = port.cell;
}
+ if (!d_lut) return false;
if (index.query_is_output(ff.sig_q))
return false;
@@ -167,6 +169,7 @@ struct OptFfInvWorker
log_assert(q_inv == nullptr);
q_inv = port.cell;
}
+ if (!q_inv) return false;
ff.flip_rst_bits({0});
ff.sig_q = q_inv->getPort(ID::Y);
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 234671df5..fd56786f2 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -302,7 +302,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
ce.assign_map.apply(rstval);
ce.assign_map.apply(sig);
- if (rstval == sig) {
+ if (rstval == sig && sync_level) {
if (sync_level->type == RTLIL::SyncType::ST1)
insig = mod->Mux(NEW_ID, insig, sig, sync_level->signal);
else
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 04:32:13 +0000