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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 11:08:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 11:27:48 +0200 |
| commit | 7bd2d1064f2eceddc3c93c121c4154a2f594a040 (patch) | |
| tree | 563de1df5e323d0f217a51e29acb56c9e9f1327d /passes/proc/proc_dff.cc | |
| parent | d86a25f145012ccb6b2048af3aae22f13b97b505 (diff) | |
| download | yosys-7bd2d1064f2eceddc3c93c121c4154a2f594a040.tar.gz yosys-7bd2d1064f2eceddc3c93c121c4154a2f594a040.tar.bz2 yosys-7bd2d1064f2eceddc3c93c121c4154a2f594a040.zip | |
Using log_assert() instead of assert()
Diffstat (limited to 'passes/proc/proc_dff.cc')
| -rw-r--r-- | passes/proc/proc_dff.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index dc310bde0..91cafe3be 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -24,7 +24,6 @@ #include <sstream> #include <stdlib.h> #include <stdio.h> -#include <assert.h> static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) { @@ -288,7 +287,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) inputs.append(it->signal); compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0); } - assert(inputs.size() == compare.size()); + log_assert(inputs.size() == compare.size()); RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne"); cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); |