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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:02:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:02:53 -0700 |
| commit | c497114e94286c06fe16a6ae32e2873578a861f4 (patch) | |
| tree | ae3c87b108b6b4a4ad98700b221e7dd763f9398b /passes/pmgen | |
| parent | 44a35015b308adbbf5f87408d2928a36245f57e7 (diff) | |
| download | yosys-c497114e94286c06fe16a6ae32e2873578a861f4.tar.gz yosys-c497114e94286c06fe16a6ae32e2873578a861f4.tar.bz2 yosys-c497114e94286c06fe16a6ae32e2873578a861f4.zip | |
Another oops
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index b03fff8ec..66fe7736b 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -101,7 +101,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) SigSpec Q = st.ffM->getPort("\\Q"); P.replace(pm.sigmap(D), Q); cell->setParam("\\MREG", State::S1); - if (st.ffP->type == "$dff") + if (st.ffM->type == "$dff") cell->setPort("\\CEM", State::S1); //else if (st.ffP->type == "$dffe") // cell->setPort("\\CEM", st.ffM->getPort("\\EN")); |