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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:01:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:01:38 -0700 |
| commit | 44a35015b308adbbf5f87408d2928a36245f57e7 (patch) | |
| tree | 0036e361a7de1054018639cf208e5783d58e8ca4 /passes/pmgen | |
| parent | d508dc2906f27b088e9c1c40e7cf2f475e80c15b (diff) | |
| download | yosys-44a35015b308adbbf5f87408d2928a36245f57e7.tar.gz yosys-44a35015b308adbbf5f87408d2928a36245f57e7.tar.bz2 yosys-44a35015b308adbbf5f87408d2928a36245f57e7.zip | |
Update commented out
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 105ad1fa1..b03fff8ec 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -104,7 +104,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) if (st.ffP->type == "$dff") cell->setPort("\\CEM", State::S1); //else if (st.ffP->type == "$dffe") - // cell->setPort("\\CEP", st.ffP->getPort("\\EN")); + // cell->setPort("\\CEM", st.ffM->getPort("\\EN")); else log_abort(); } if (st.ffP) { |