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| author | Clifford Wolf <clifford@clifford.at> | 2013-05-23 16:17:23 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-05-23 16:17:23 +0200 |
| commit | 585fcace10d589c87014debc61ecd1c4e40d8159 (patch) | |
| tree | 4d09d8cff3ad3bc5980503bc599036778ddc13c3 /passes/abc | |
| parent | f674150f1c5200f76e0f23739b06fde6a143bb6d (diff) | |
| download | yosys-585fcace10d589c87014debc61ecd1c4e40d8159.tar.gz yosys-585fcace10d589c87014debc61ecd1c4e40d8159.tar.bz2 yosys-585fcace10d589c87014debc61ecd1c4e40d8159.zip | |
Fixed a gcc vs. clang determinism problem in abc pass
Diffstat (limited to 'passes/abc')
| -rw-r--r-- | passes/abc/abc.cc | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index ccf0fccb3..9a13a446b 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -123,12 +123,15 @@ static void extract_cell(RTLIL::Cell *cell) assign_map.apply(sig_b); assign_map.apply(sig_y); + int mapped_a = map_signal(sig_a); + int mapped_b = map_signal(sig_b); + if (cell->type == "$_AND_") - map_signal(sig_y, 'a', map_signal(sig_a), map_signal(sig_b)); + map_signal(sig_y, 'a', mapped_a, mapped_b); else if (cell->type == "$_OR_") - map_signal(sig_y, 'o', map_signal(sig_a), map_signal(sig_b)); + map_signal(sig_y, 'o', mapped_a, mapped_b); else if (cell->type == "$_XOR_") - map_signal(sig_y, 'x', map_signal(sig_a), map_signal(sig_b)); + map_signal(sig_y, 'x', mapped_a, mapped_b); else abort(); @@ -149,7 +152,11 @@ static void extract_cell(RTLIL::Cell *cell) assign_map.apply(sig_s); assign_map.apply(sig_y); - map_signal(sig_y, 'm', map_signal(sig_a), map_signal(sig_b), map_signal(sig_s)); + int mapped_a = map_signal(sig_a); + int mapped_b = map_signal(sig_b); + int mapped_s = map_signal(sig_s); + + map_signal(sig_y, 'm', mapped_a, mapped_b, mapped_s); module->cells.erase(cell->name); delete cell; |