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| author | Clifford Wolf <clifford@clifford.at> | 2014-10-16 10:31:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-16 10:31:54 +0200 |
| commit | 3838856a9ee6debb05f39ad2c17d2eba95afd329 (patch) | |
| tree | 84ed58cdd77aa81fd2f602db0ccfada4a7fa5fa5 /passes/abc | |
| parent | 3be5fa053f61a29039ed99876d3e89406c99cb7d (diff) | |
| download | yosys-3838856a9ee6debb05f39ad2c17d2eba95afd329.tar.gz yosys-3838856a9ee6debb05f39ad2c17d2eba95afd329.tar.bz2 yosys-3838856a9ee6debb05f39ad2c17d2eba95afd329.zip | |
Print "SystemVerilog" in "read_verilog -sv" log messages
Diffstat (limited to 'passes/abc')
0 files changed, 0 insertions, 0 deletions