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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-08 14:25:29 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-08 14:25:29 +0100 |
| commit | 03ee63ff80dae4eefc463975f183b501a1f98c95 (patch) | |
| tree | e093c2a427a4494a070cf1ff6113681f0b5d68ba /passes/abc | |
| parent | 82c98bbbe60eb9246d399e712e92e4ff514402fa (diff) | |
| download | yosys-03ee63ff80dae4eefc463975f183b501a1f98c95.tar.gz yosys-03ee63ff80dae4eefc463975f183b501a1f98c95.tar.bz2 yosys-03ee63ff80dae4eefc463975f183b501a1f98c95.zip | |
Added support for "keep" attribute to abc pass
Diffstat (limited to 'passes/abc')
| -rw-r--r-- | passes/abc/abc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 8f873867d..5aa13572e 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -447,7 +447,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std extract_cell(c); for (auto &wire_it : module->wires) { - if (wire_it.second->port_id > 0) + if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep")) mark_port(RTLIL::SigSpec(wire_it.second)); } |