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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-21 17:03:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 7146c0339e0b79ec24bc89e7fdf15331436e0e53 (patch) | |
| tree | cec9a7305b6ed1d46c043f43bdb9fabce07c6553 /kernel/timinginfo.h | |
| parent | 6c34945371a0446159423b0d70f9f10dbc2c4d07 (diff) | |
| download | yosys-7146c0339e0b79ec24bc89e7fdf15331436e0e53.tar.gz yosys-7146c0339e0b79ec24bc89e7fdf15331436e0e53.tar.bz2 yosys-7146c0339e0b79ec24bc89e7fdf15331436e0e53.zip | |
timinginfo: ignore $specify2 cells if EN is false
Diffstat (limited to 'kernel/timinginfo.h')
| -rw-r--r-- | kernel/timinginfo.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index 36908868c..d818e580b 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -82,6 +82,9 @@ struct TimingInfo for (auto cell : module->cells()) { if (cell->type == ID($specify2)) { + auto en = cell->getPort(ID::EN); + if (en.is_fully_const() && !en.as_bool()) + continue; auto src = cell->getPort(ID::SRC); auto dst = cell->getPort(ID::DST); for (const auto &c : src.chunks()) |