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author | Eddie Hung <eddie@fpgeh.com> | 2020-04-21 15:45:05 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
commit | 6c34945371a0446159423b0d70f9f10dbc2c4d07 (patch) | |
tree | 0f8cdc9be3d28a681eaee006442d6e65d9b92f79 /kernel/timinginfo.h | |
parent | b65610fb628cfd38edcab3c64507477a58cbdd10 (diff) | |
download | yosys-6c34945371a0446159423b0d70f9f10dbc2c4d07.tar.gz yosys-6c34945371a0446159423b0d70f9f10dbc2c4d07.tar.bz2 yosys-6c34945371a0446159423b0d70f9f10dbc2c4d07.zip |
xilinx/ice40/ecp5: zinit requires selected wires, so select them all
Diffstat (limited to 'kernel/timinginfo.h')
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