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| author | Clifford Wolf <clifford@clifford.at> | 2016-06-19 15:48:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-06-19 15:48:40 +0200 |
| commit | 9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68 (patch) | |
| tree | 74840e34ae02c49884e81916eb81be4fd93c006d /kernel/rtlil.cc | |
| parent | ca91bccb6b03a0b098f80bf14b55a1444eef73c0 (diff) | |
| parent | a8200a773fb8cf2ce2d8793716b62e01c97dd731 (diff) | |
| download | yosys-9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68.tar.gz yosys-9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68.tar.bz2 yosys-9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68.zip | |
Merge branch 'sv_packages' of https://github.com/rubund/yosys
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index bcd87d3ff..9da6d2816 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -304,6 +304,8 @@ RTLIL::Design::~Design() { for (auto it = modules_.begin(); it != modules_.end(); ++it) delete it->second; + for (auto n : verilog_packages) + delete n; } RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules() |