From 178ff3e7f6f9766f0b1a3e8dcc96e030aea59b15 Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Sat, 18 Jun 2016 10:24:21 +0200 Subject: Added support for SystemVerilog packages with localparam definitions --- kernel/rtlil.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'kernel/rtlil.cc') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index bcd87d3ff..9e09d9f04 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -304,6 +304,8 @@ RTLIL::Design::~Design() { for (auto it = modules_.begin(); it != modules_.end(); ++it) delete it->second; + for (auto n : packages) + delete n; } RTLIL::ObjRange RTLIL::Design::modules() -- cgit v1.2.3 From a8200a773fb8cf2ce2d8793716b62e01c97dd731 Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Sat, 18 Jun 2016 14:13:36 +0200 Subject: A few modifications after pull request comments - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel/rtlil.cc') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9e09d9f04..9da6d2816 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -304,7 +304,7 @@ RTLIL::Design::~Design() { for (auto it = modules_.begin(); it != modules_.end(); ++it) delete it->second; - for (auto n : packages) + for (auto n : verilog_packages) delete n; } -- cgit v1.2.3