Added module->design and cell->module, wire->module pointers

4 files changed, 11 insertions, 11 deletions

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index d548a679c..46b717ce0 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -936,7 +936,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 			(*it)->str = (*it)->str.substr(1);
 		if (defer)
 			(*it)->str = "$abstract" + (*it)->str;
-		if (design->modules_.count((*it)->str)) {
+		if (design->has((*it)->str)) {
 			if (!ignore_redef)
 				log_error("Re-definition of module `%s' at %s:%d!\n",
 						(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
@@ -944,7 +944,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 					(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
 			continue;
 		}
-		design->modules_[(*it)->str] =  process_module(*it, defer);
+		design->add(process_module(*it, defer));
 	}
 }
 
@@ -1041,10 +1041,10 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
 		modname = "$paramod" + stripped_name + para_info;
 	}
 
-	if (design->modules_.count(modname) == 0) {
+	if (!design->has(modname)) {
 		new_ast->str = modname;
-		design->modules_[modname] = process_module(new_ast, false);
-		design->modules_[modname]->check();
+		design->add(process_module(new_ast, false));
+		design->module(modname)->check();
 	} else {
 		log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
 	}
diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y
index ab763b2b1..67cc7da78 100644
--- a/frontends/ilang/parser.y
+++ b/frontends/ilang/parser.y
@@ -90,12 +90,12 @@ design:
 
 module:
 	TOK_MODULE TOK_ID EOL {
-		if (current_design->modules_.count($2) != 0)
+		if (current_design->has($2))
 			rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
 		current_module = new RTLIL::Module;
 		current_module->name = $2;
 		current_module->attributes = attrbuf;
-		current_design->modules_[$2] = current_module;
+		current_design->add(current_module);
 		attrbuf.clear();
 		free($2);
 	} module_body TOK_END {
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index da16ab33f..d3168ab8e 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -477,7 +477,7 @@ struct LibertyFrontend : public Frontend {
 
 			std::string cell_name = RTLIL::escape_id(cell->args.at(0));
 
-			if (design->modules_.count(cell_name)) {
+			if (design->has(cell_name)) {
 				if (flag_ignore_redef)
 					continue;
 				log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name));
@@ -565,7 +565,7 @@ struct LibertyFrontend : public Frontend {
 			}
 
 			module->fixup_ports();
-			design->modules_[module->name] = module;
+			design->add(module);
 			cell_count++;
 skip_cell:;
 		}
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 6e692c5a1..c7b99c7a9 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -482,7 +482,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 {
 	std::string module_name = nl->IsOperator() ? std::string("$verific$") + nl->Owner()->Name() : RTLIL::escape_id(nl->Owner()->Name());
 
-	if (design->modules_.count(module_name)) {
+	if (design->has(module_name)) {
 		if (!nl->IsOperator())
 			log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name());
 		return;
@@ -490,7 +490,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 
 	RTLIL::Module *module = new RTLIL::Module;
 	module->name = module_name;
-	design->modules_[module->name] = module;
+	design->add(module);
 
 	log("Importing module %s.\n", RTLIL::id2cstr(module->name));