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| author | Clifford Wolf <clifford@clifford.at> | 2016-02-02 11:26:07 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-02-02 11:26:07 +0100 |
| commit | ba407da18793981289d6fa444071a0c8628cb5f3 (patch) | |
| tree | a522c74513ff13a331a6cb19e72bc97fbf7c4732 /frontends | |
| parent | d6592d5b996b1b5af1af701e32cc74694cd491ef (diff) | |
| download | yosys-ba407da18793981289d6fa444071a0c8628cb5f3.tar.gz yosys-ba407da18793981289d6fa444071a0c8628cb5f3.tar.bz2 yosys-ba407da18793981289d6fa444071a0c8628cb5f3.zip | |
Added addBufGate module method
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 45cd4f3fc..1ec6a7c0a 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -186,6 +186,11 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*, return true; } + if (inst->Type() == PRIM_BUF) { + module->addBufGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput())); + return true; + } + if (inst->Type() == PRIM_INV) { module->addNotGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput())); return true; |