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author | Clifford Wolf <clifford@clifford.at> | 2016-11-15 12:42:43 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-11-15 12:42:43 +0100 |
commit | a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51 (patch) | |
tree | effa1745fb6b7c2320455c2d4f7c58171e8edab1 /frontends | |
parent | a2206180d60c857578209300c3a693e9c4723459 (diff) | |
download | yosys-a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51.tar.gz yosys-a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51.tar.bz2 yosys-a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51.zip |
Remember global declarations and defines accross read_verilog calls
Diffstat (limited to 'frontends')
-rw-r--r-- | frontends/ast/ast.cc | 6 | ||||
-rw-r--r-- | frontends/verilog/preproc.cc | 15 | ||||
-rw-r--r-- | frontends/verilog/verilog_frontend.cc | 2 | ||||
-rw-r--r-- | frontends/verilog/verilog_frontend.h | 3 |
4 files changed, 19 insertions, 7 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 92513a244..5b4a4af47 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1016,14 +1016,12 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump flag_icells = icells; flag_autowire = autowire; - std::vector<AstNode*> global_decls; - log_assert(current_ast->type == AST_DESIGN); for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) { if ((*it)->type == AST_MODULE) { - for (auto n : global_decls) + for (auto n : design->verilog_globals) (*it)->children.push_back(n->clone()); for (auto n : design->verilog_packages){ @@ -1054,7 +1052,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump else if ((*it)->type == AST_PACKAGE) design->verilog_packages.push_back((*it)->clone()); else - global_decls.push_back(*it); + design->verilog_globals.push_back((*it)->clone()); } } diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 997920b89..0c6cfc6ac 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -210,7 +210,8 @@ static void input_file(std::istream &f, std::string filename) input_buffer.insert(it, "\n`file_pop\n"); } -std::string frontend_verilog_preproc(std::istream &f, std::string filename, const std::map<std::string, std::string> pre_defines_map, const std::list<std::string> include_dirs) +std::string frontend_verilog_preproc(std::istream &f, std::string filename, const std::map<std::string, std::string> &pre_defines_map, + dict<std::string, std::pair<std::string, bool>> &global_defines_cache, const std::list<std::string> &include_dirs) { std::set<std::string> defines_with_args; std::map<std::string, std::string> defines_map(pre_defines_map); @@ -222,9 +223,19 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons input_buffer_charp = 0; input_file(f, filename); + defines_map["YOSYS"] = "1"; defines_map[formal_mode ? "FORMAL" : "SYNTHESIS"] = "1"; + for (auto &it : pre_defines_map) + defines_map[it.first] = it.second; + + for (auto &it : global_defines_cache) { + if (it.second.second) + defines_with_args.insert(it.first); + defines_map[it.first] = it.second.first; + } + while (!input_buffer.empty()) { std::string tok = next_token(); @@ -379,6 +390,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons defines_with_args.insert(name); else defines_with_args.erase(name); + global_defines_cache[name] = std::pair<std::string, bool>(value, state == 2); continue; } @@ -389,6 +401,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons // printf("undef: >>%s<<\n", name.c_str()); defines_map.erase(name); defines_with_args.erase(name); + global_defines_cache.erase(name); continue; } diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 894723c85..3c9ed7ee3 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -345,7 +345,7 @@ struct VerilogFrontend : public Frontend { std::string code_after_preproc; if (!flag_nopp) { - code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, include_dirs); + code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, design->verilog_defines, include_dirs); if (flag_ppdump) log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str()); lexin = new std::istringstream(code_after_preproc); diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index 606ec20a2..16edc7985 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -68,7 +68,8 @@ namespace VERILOG_FRONTEND } // the pre-processor -std::string frontend_verilog_preproc(std::istream &f, std::string filename, const std::map<std::string, std::string> pre_defines_map, const std::list<std::string> include_dirs); +std::string frontend_verilog_preproc(std::istream &f, std::string filename, const std::map<std::string, std::string> &pre_defines_map, + dict<std::string, std::pair<std::string, bool>> &global_defines_cache, const std::list<std::string> &include_dirs); YOSYS_NAMESPACE_END |