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| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-10-21 12:13:35 +0200 |
|---|---|---|
| committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-10-21 12:13:35 +0200 |
| commit | 90b440f870a8ac2c91b3f716f38a4f538cad2549 (patch) | |
| tree | e293a349c65f26c69cfe6f735301b90b8ae0f5d9 /frontends | |
| parent | 16a177560f27c77ba490ac7dbe9eae3d3766ca1e (diff) | |
| download | yosys-90b440f870a8ac2c91b3f716f38a4f538cad2549.tar.gz yosys-90b440f870a8ac2c91b3f716f38a4f538cad2549.tar.bz2 yosys-90b440f870a8ac2c91b3f716f38a4f538cad2549.zip | |
Fix verific.cc PRIM_DLATCH handling
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 6b303e4b6..18fba9b76 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -443,7 +443,13 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr if (inst->Type() == PRIM_DLATCH) { - module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput())); + if (inst->GetAsyncCond()->IsGnd()) { + module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput())); + } else { + RTLIL::SigSpec sig_set = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal())); + RTLIL::SigSpec sig_clr = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEW_ID, net_map_at(inst->GetAsyncVal()))); + module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_clr, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput())); + } return true; } |