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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 14:23:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 14:23:39 -0700 |
| commit | 848b023ccccc0cffa70d1aea45e558bdabb207b9 (patch) | |
| tree | dd2ec1c9dd710f90ac1037a9e88ca7a25ea36ef7 /frontends | |
| parent | 8f59afd62d6d28059efb6caad1232254146daddd (diff) | |
| download | yosys-848b023ccccc0cffa70d1aea45e558bdabb207b9.tar.gz yosys-848b023ccccc0cffa70d1aea45e558bdabb207b9.tar.bz2 yosys-848b023ccccc0cffa70d1aea45e558bdabb207b9.zip | |
Workaround issues exposed by gcc-4.8
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index d50a38b7a..5f236992d 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -114,13 +114,20 @@ struct ConstEvalAig RTLIL::Cell *cell = sig2driver.at(output); RTLIL::SigBit sig_a = cell->getPort("\\A"); + sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation + // that may occur does so here, and + // not mid insertion (below) sig2deps[sig_a].insert(sig2deps[output].begin(), sig2deps[output].end()); if (!inputs.count(sig_a)) compute_deps(sig_a, inputs); if (cell->type == "$_AND_") { RTLIL::SigSpec sig_b = cell->getPort("\\B"); + sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation + // that may occur does so here, and + // not mid insertion (below) sig2deps[sig_b].insert(sig2deps[output].begin(), sig2deps[output].end()); + if (!inputs.count(sig_b)) compute_deps(sig_b, inputs); } |