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| author | Clifford Wolf <clifford@clifford.at> | 2016-02-13 08:19:30 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-02-13 08:19:30 +0100 |
| commit | 7bd329afa07ad97969afa69faba925634b03252d (patch) | |
| tree | 7086d7162fe922df0a614e5480554face0660605 /frontends | |
| parent | 840a6dc893221119a9aed52b8294445e48a964a9 (diff) | |
| download | yosys-7bd329afa07ad97969afa69faba925634b03252d.tar.gz yosys-7bd329afa07ad97969afa69faba925634b03252d.tar.bz2 yosys-7bd329afa07ad97969afa69faba925634b03252d.zip | |
Support for more Verific primitives (patch I got per email)
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index d2440f699..b0fdedccd 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -186,6 +186,11 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*, return true; } + if (inst->Type() == PRIM_XNOR) { + module->addXnorGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), net_map.at(inst->GetOutput())); + return true; + } + if (inst->Type() == PRIM_BUF) { module->addBufGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput())); return true; @@ -374,6 +379,26 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*, return true; } + if (inst->Type() == OPER_ENABLED_DECODER) { + RTLIL::SigSpec vec; + vec.append(net_map.at(inst->GetControl())); + for (unsigned i = 1; i < inst->OutputSize(); i++) { + vec.append(RTLIL::State::S0); + } + module->addShl(RTLIL::escape_id(inst->Name()), vec, IN, OUT, false); + return true; + } + + if (inst->Type() == OPER_DECODER) { + RTLIL::SigSpec vec; + vec.append(RTLIL::State::S1); + for (unsigned i = 1; i < inst->OutputSize(); i++) { + vec.append(RTLIL::State::S0); + } + module->addShl(RTLIL::escape_id(inst->Name()), vec, IN, OUT, false); + return true; + } + if (inst->Type() == OPER_SHIFT_RIGHT) { Net *net_cin = inst->GetCin(); Net *net_a_msb = inst->GetInput1Bit(0); @@ -681,6 +706,11 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist* continue; } + if (inst->Type() == PRIM_BUF) { + module->addBufGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput())); + continue; + } + if (inst->Type() == PRIM_X) { module->connect(net_map.at(inst->GetOutput()), RTLIL::State::Sx); continue; @@ -753,7 +783,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist* } if (inst->IsPrimitive()) - log_error("Unsupported Verific primitive: %s\n", inst->View()->Owner()->Name()); + log_error("Unsupported Verific primitive %s of type %s\n", inst->Name(), inst->View()->Owner()->Name()); nl_todo.insert(inst->View()); |