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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-02 11:36:26 +0200 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-07-09 18:46:28 +0100 |
| commit | 7b298479d4a10ac20379955fa749e70560b72b7f (patch) | |
| tree | 4c44e19d0c728bee0538439648c7a26ef166fb6f /frontends | |
| parent | fc87c010c504863b242b8882c1170396a7d1d43c (diff) | |
| download | yosys-7b298479d4a10ac20379955fa749e70560b72b7f.tar.gz yosys-7b298479d4a10ac20379955fa749e70560b72b7f.tar.bz2 yosys-7b298479d4a10ac20379955fa749e70560b72b7f.zip | |
Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index d3fd91473..951d9c66f 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some global state.. its a mess) */ [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] { + if (!strcmp(yytext, "default")) + return TOK_DEFAULT; frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); return TOK_SVA_LABEL; } |