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| author | Claire Wolf <claire@symbioticeda.com> | 2020-07-15 11:54:28 +0200 |
|---|---|---|
| committer | Claire Wolf <claire@symbioticeda.com> | 2020-07-15 11:54:28 +0200 |
| commit | 7a79843cc394f59bdd40473a823c7f60c87d3fa6 (patch) | |
| tree | 1619e79e43105251f86e3c9314d0086a5444ff5d /frontends | |
| parent | 24540291c7b3b42518dfbea9ec59c9b681d0e54e (diff) | |
| download | yosys-7a79843cc394f59bdd40473a823c7f60c87d3fa6.tar.gz yosys-7a79843cc394f59bdd40473a823c7f60c87d3fa6.tar.bz2 yosys-7a79843cc394f59bdd40473a823c7f60c87d3fa6.zip | |
Use %precedence in verilog_parser.y
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 390ef07e9..63f0341d9 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -299,14 +299,14 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode) %left '+' '-' %left '*' '/' '%' %left OP_POW -%left OP_CAST -%right UNARY_OPS +%precedence OP_CAST +%precedence UNARY_OPS %define parse.error verbose %define parse.lac full -%nonassoc FAKE_THEN -%nonassoc TOK_ELSE +%precedence FAKE_THEN +%precedence TOK_ELSE %debug %locations |