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| author | Clifford Wolf <clifford@clifford.at> | 2016-04-22 18:02:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-04-22 18:02:55 +0200 |
| commit | 779e2cc819463fa5bc4ebfee397eb06368eb10b0 (patch) | |
| tree | 927f9f25f6d3a8469ed732290cbd263bda97de72 /frontends | |
| parent | 60ac1bd178eef96b5cc34091dca7552cc3cad70f (diff) | |
| download | yosys-779e2cc819463fa5bc4ebfee397eb06368eb10b0.tar.gz yosys-779e2cc819463fa5bc4ebfee397eb06368eb10b0.tar.bz2 yosys-779e2cc819463fa5bc4ebfee397eb06368eb10b0.zip | |
Added support for "active high" and "active low" latches in BLIF front-end
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/blif/blifparse.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index a028c4336..a901e55f9 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -244,6 +244,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); else if (!strcmp(edge, "fe")) cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); + else if (!strcmp(edge, "ah")) + cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); + else if (!strcmp(edge, "al")) + cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); else { no_latch_clock: cell = module->addCell(NEW_ID, dff_name); |