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| author | Clifford Wolf <clifford@clifford.at> | 2016-02-03 08:59:57 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-02-03 08:59:57 +0100 |
| commit | 6a27cbe5b17b012aef904bc31c13d8a2b0b15f01 (patch) | |
| tree | 5c1abdc8d97299dcacf2c47226c6bd93ad14b3b4 /frontends | |
| parent | 4a3e1ded1e2dfd3d9a836aaed793978ddff6161b (diff) | |
| download | yosys-6a27cbe5b17b012aef904bc31c13d8a2b0b15f01.tar.gz yosys-6a27cbe5b17b012aef904bc31c13d8a2b0b15f01.tar.bz2 yosys-6a27cbe5b17b012aef904bc31c13d8a2b0b15f01.zip | |
Bugfix in Verific front-end
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 1ec6a7c0a..d2440f699 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -773,8 +773,11 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist* } IdString port_name_id = RTLIL::escape_id(port_name); auto &sigvec = cell_port_conns[port_name_id]; - if (GetSize(sigvec) <= port_offset) - sigvec.resize(port_offset+1, State::Sz); + if (GetSize(sigvec) <= port_offset) { + SigSpec zwires = module->addWire(NEW_ID, port_offset+1-GetSize(sigvec)); + for (auto bit : zwires) + sigvec.push_back(bit); + } sigvec[port_offset] = net_map.at(pr->GetNet()); } |