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| author | N. Engelhardt <nak@yosyshq.com> | 2022-04-15 15:10:48 +0200 |
|---|---|---|
| committer | N. Engelhardt <nak@yosyshq.com> | 2022-04-15 15:10:48 +0200 |
| commit | 57bc29c64a546fc1dc9a14f0d19a1e30fb5948f0 (patch) | |
| tree | 25899c24a1326155d69859ff152929b7d63ca783 /frontends | |
| parent | c1646a00ac5a7b6ab53af64d5f2f70c5848cdf12 (diff) | |
| download | yosys-57bc29c64a546fc1dc9a14f0d19a1e30fb5948f0.tar.gz yosys-57bc29c64a546fc1dc9a14f0d19a1e30fb5948f0.tar.bz2 yosys-57bc29c64a546fc1dc9a14f0d19a1e30fb5948f0.zip | |
verific: allow memories to be inferred in loops
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 44196a310..b53bad7da 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2548,6 +2548,7 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); + RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); #ifdef VERIFIC_VHDL_SUPPORT RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); |