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| author | whitequark <whitequark@whitequark.org> | 2021-02-05 06:49:34 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-05 06:49:34 +0000 |
| commit | 3d9898272a5afd60f6080603bf065056d9dca000 (patch) | |
| tree | 600f7d8df8c2d9958053b56f60a3135c712c1e3d /frontends | |
| parent | 7c6bf42db8cf8e269b04591a80d8e085e072059a (diff) | |
| parent | 98c4feb72ff52f12aadd34b0deccb819d701ff2c (diff) | |
| download | yosys-3d9898272a5afd60f6080603bf065056d9dca000.tar.gz yosys-3d9898272a5afd60f6080603bf065056d9dca000.tar.bz2 yosys-3d9898272a5afd60f6080603bf065056d9dca000.zip | |
Merge pull request #2572 from antmicro/check-labels
verilog_parser: add label check to gen_block
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 6255a4204..fb5846f7b 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2794,6 +2794,8 @@ gen_block: ast_stack.push_back(node); } module_gen_body TOK_END opt_label { exitTypeScope(); + if ($3 != NULL && $7 != NULL && *$3 != *$7) + frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1); delete $3; delete $7; SET_AST_NODE_LOC(ast_stack.back(), @1, @7); |