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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 12:37:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 12:37:42 -0700 |
| commit | 3732d421c569a600535734fe63b862b6bc852b82 (patch) | |
| tree | f5311ab477565470c955f574cf8fb8204ea46245 /frontends | |
| parent | e67e4a5ed66df59f5f924e6bb3891f87fc93f070 (diff) | |
| parent | 8c1a98249457b790895aee76115ddd40ec891555 (diff) | |
| download | yosys-3732d421c569a600535734fe63b862b6bc852b82.tar.gz yosys-3732d421c569a600535734fe63b862b6bc852b82.tar.bz2 yosys-3732d421c569a600535734fe63b862b6bc852b82.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/ast.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 82283fb5b..a3a78e414 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1099,6 +1099,13 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast ignoreThisSignalsInInitial = RTLIL::SigSpec(); } + else { + for (auto &attr : ast->attributes) { + if (attr.second->type != AST_CONSTANT) + continue; + current_module->attributes[attr.first] = attr.second->asAttrConst(); + } + } if (ast->type == AST_INTERFACE) current_module->set_bool_attribute("\\is_interface"); |