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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-11 17:10:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-11 17:10:47 -0700 |
| commit | 2dffa4685b830313204f5d04314a14ed6ecac8ec (patch) | |
| tree | 023b8e9760f344f59f26efbe3912c3f610ff8bfe /frontends | |
| parent | d26646051c4ae9740decd5d76eec6a3afd63844a (diff) | |
| download | yosys-2dffa4685b830313204f5d04314a14ed6ecac8ec.tar.gz yosys-2dffa4685b830313204f5d04314a14ed6ecac8ec.tar.bz2 yosys-2dffa4685b830313204f5d04314a14ed6ecac8ec.zip | |
Add "-W' wire delay arg to abc9, use from synth_xilinx
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 3c612472d..9558bbfb9 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -311,11 +311,6 @@ supply1 { return TOK_SUPPLY1; } return TOK_ID; } -"$"(info|warning|error|fatal) { - frontend_verilog_yylval.string = new std::string(yytext); - return TOK_ELAB_TASK; -} - "$signed" { return TOK_TO_SIGNED; } "$unsigned" { return TOK_TO_UNSIGNED; } |