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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-18 09:10:28 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-18 09:10:28 +0200 |
| commit | 1cc281ca6fc4035a8f48fd7b7a0289cb580c3f4c (patch) | |
| tree | 445cdb3c9e0712fad8473c76775b3f2b554e5729 /frontends | |
| parent | d23260d381a1b58ff7f0a0ce65e1884e2ceaa05d (diff) | |
| download | yosys-1cc281ca6fc4035a8f48fd7b7a0289cb580c3f4c.tar.gz yosys-1cc281ca6fc4035a8f48fd7b7a0289cb580c3f4c.tar.bz2 yosys-1cc281ca6fc4035a8f48fd7b7a0289cb580c3f4c.zip | |
verific: allow memories to be inferred in loops (vhdl)
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index b53bad7da..284d5db31 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2553,6 +2553,7 @@ struct VerificPass : public Pass { #ifdef VERIFIC_VHDL_SUPPORT RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1); + RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1); RuntimeFlags::SetVar("vhdl_support_variable_slice", 1); RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); |