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| author | Clifford Wolf <clifford@clifford.at> | 2013-06-13 11:18:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-13 11:18:45 +0200 |
| commit | 0c6ffc4c656de69c92727580cd4c192211d10e6d (patch) | |
| tree | 9ad133c4d71f687f1046692e1a80481d3d114a89 /frontends | |
| parent | b1d39aa8656f8440eb748fbc7b5673d2129a2308 (diff) | |
| download | yosys-0c6ffc4c656de69c92727580cd4c192211d10e6d.tar.gz yosys-0c6ffc4c656de69c92727580cd4c192211d10e6d.tar.bz2 yosys-0c6ffc4c656de69c92727580cd4c192211d10e6d.zip | |
More fixes for bugs found using xsthammer
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 6 | ||||
| -rw-r--r-- | frontends/verilog/lexer.l | 4 | ||||
| -rw-r--r-- | frontends/verilog/parser.y | 14 |
3 files changed, 16 insertions, 8 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index cb59246c6..aa5a98c41 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -752,7 +752,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint) RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint); is_signed = type == AST_NEG || (type == AST_POS && children[0]->is_signed); int width = type == AST_NEG && arg.width < width_hint ? arg.width+1 : arg.width; - if (width > width_hint && width_hint > 0) + if (width_hint > 0) width = width_hint; return uniop2rtlil(this, type_name, width, arg); } @@ -766,9 +766,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint) RTLIL::SigSpec left = children[0]->genRTLIL(width_hint); RTLIL::SigSpec right = children[1]->genRTLIL(width_hint); int width = std::max(left.width, right.width); - if (width > width_hint && width_hint > 0) - width = width_hint; - if (width < width_hint) + if (width_hint > 0) width = width_hint; return binop2rtlil(this, type_name, width, left, right); } diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l index 783b790b0..78f1d3674 100644 --- a/frontends/verilog/lexer.l +++ b/frontends/verilog/lexer.l @@ -236,8 +236,8 @@ supply1 { return TOK_SUPPLY1; } "===" { return OP_EQ; } "!==" { return OP_NE; } - /* "~&" { return OP_NAND; } */ - /* "~|" { return OP_NOR; } */ +"~&" { return OP_NAND; } +"~|" { return OP_NOR; } "~^" { return OP_XNOR; } "^~" { return OP_XNOR; } diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index ea39e83d4..68ac26bf9 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -113,9 +113,9 @@ static void free_attr(std::map<std::string, AstNode*> *al) // operator precedence from low to high %left OP_LOR %left OP_LAND -%left '|' +%left '|' OP_NOR %left '^' OP_XNOR -%left '&' +%left '&' OP_NAND %left OP_EQ OP_NE %left '<' OP_LE OP_GE '>' %left OP_SHL OP_SHR OP_SSHL OP_SSHR @@ -982,10 +982,20 @@ basic_expr: $$ = new AstNode(AST_REDUCE_AND, $3); append_attr($$, $2); } | + OP_NAND attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_REDUCE_AND, $3); + append_attr($$, $2); + $$ = new AstNode(AST_LOGIC_NOT, $$); + } | '|' attr basic_expr %prec UNARY_OPS { $$ = new AstNode(AST_REDUCE_OR, $3); append_attr($$, $2); } | + OP_NOR attr basic_expr %prec UNARY_OPS { + $$ = new AstNode(AST_REDUCE_OR, $3); + append_attr($$, $2); + $$ = new AstNode(AST_LOGIC_NOT, $$); + } | '^' attr basic_expr %prec UNARY_OPS { $$ = new AstNode(AST_REDUCE_XOR, $3); append_attr($$, $2); |