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| author | Clifford Wolf <clifford@clifford.at> | 2017-04-07 09:58:54 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-04-07 09:58:54 +0200 |
| commit | 7791888703a72880679ebe8ae3bbdc63db8f00e2 (patch) | |
| tree | f474149e35f09f18cc6ff701ec03c667bd76477c /examples/intel/asicworld_lfsr/runme_presynth | |
| parent | fcb274a5644016c4090cdfbfbd795f311a7e58f5 (diff) | |
| parent | c27dcc1e47fa00cd415893c9d3f637a5d5865988 (diff) | |
| download | yosys-7791888703a72880679ebe8ae3bbdc63db8f00e2.tar.gz yosys-7791888703a72880679ebe8ae3bbdc63db8f00e2.tar.bz2 yosys-7791888703a72880679ebe8ae3bbdc63db8f00e2.zip | |
Merge pull request #337 from dh73/master
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
Diffstat (limited to 'examples/intel/asicworld_lfsr/runme_presynth')
| -rwxr-xr-x | examples/intel/asicworld_lfsr/runme_presynth | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/examples/intel/asicworld_lfsr/runme_presynth b/examples/intel/asicworld_lfsr/runme_presynth new file mode 100755 index 000000000..51118bb4b --- /dev/null +++ b/examples/intel/asicworld_lfsr/runme_presynth @@ -0,0 +1,5 @@ +#!/bin/bash + +iverilog -o presynth lfsr_updown_tb.v lfsr_updown.v &&\ + +vvp -N presynth
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