From c27dcc1e47fa00cd415893c9d3f637a5d5865988 Mon Sep 17 00:00:00 2001 From: dh73 Date: Wed, 5 Apr 2017 23:01:29 -0500 Subject: Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs --- examples/intel/asicworld_lfsr/runme_presynth | 5 +++++ 1 file changed, 5 insertions(+) create mode 100755 examples/intel/asicworld_lfsr/runme_presynth (limited to 'examples/intel/asicworld_lfsr/runme_presynth') diff --git a/examples/intel/asicworld_lfsr/runme_presynth b/examples/intel/asicworld_lfsr/runme_presynth new file mode 100755 index 000000000..51118bb4b --- /dev/null +++ b/examples/intel/asicworld_lfsr/runme_presynth @@ -0,0 +1,5 @@ +#!/bin/bash + +iverilog -o presynth lfsr_updown_tb.v lfsr_updown.v &&\ + +vvp -N presynth \ No newline at end of file -- cgit v1.2.3