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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-24 11:13:32 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-24 11:13:32 +0100 |
| commit | df9753d398ff1f10396a8561524fee20fdbf512c (patch) | |
| tree | f614c10cca56acf78e3fda6a886d5ea0cdceaf96 /README | |
| parent | 6960df7285fc7f2c703f349bea841800737f8dca (diff) | |
| download | yosys-df9753d398ff1f10396a8561524fee20fdbf512c.tar.gz yosys-df9753d398ff1f10396a8561524fee20fdbf512c.tar.bz2 yosys-df9753d398ff1f10396a8561524fee20fdbf512c.zip | |
Added mem2reg option to verilog frontend
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -192,6 +192,9 @@ Verilog Attributes and non-standard features - The "nomem2reg" attribute on modules or arrays prohibits the automatic early conversion of arrays to separate registers. +- The "mem2reg" attribute on modules or arrays forces the early + conversion of arrays to separate registers. + - The "nolatches" attribute on modules or always-blocks prohibits the generation of logic-loops for latches. Instead all not explicitly assigned values default to x-bits. |