From df9753d398ff1f10396a8561524fee20fdbf512c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Mar 2013 11:13:32 +0100
Subject: Added mem2reg option to verilog frontend

---
 README | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'README')

diff --git a/README b/README
index 97f2ba9b1..59238c4ad 100644
--- a/README
+++ b/README
@@ -192,6 +192,9 @@ Verilog Attributes and non-standard features
 - The "nomem2reg" attribute on modules or arrays prohibits the
   automatic early conversion of arrays to separate registers.
 
+- The "mem2reg" attribute on modules or arrays forces the early
+  conversion of arrays to separate registers.
+
 - The "nolatches" attribute on modules or always-blocks
   prohibits the generation of logic-loops for latches. Instead
   all not explicitly assigned values default to x-bits.
-- 
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