From 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 31 Jul 2014 02:32:00 +0200
Subject: Renamed "stdcells.v" to "techmap.v"

---
 README | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'README')

diff --git a/README b/README
index 4384cfbdd..1e0ade91c 100644
--- a/README
+++ b/README
@@ -304,8 +304,7 @@ Roadmap / Large-scale TODOs
    - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
 
 - Technology mapping for real-world applications
-   - Add bit-wise const-folding via cell parameters to techmap pass
-   - Rewrite current stdcells.v techmap rules (modular and clean)
+   - Rewrite current techmap.v rules (modular and clean)
    - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)
 
 - Implement SAT-based formal equivialence checker
-- 
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