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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:00:36 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:00:36 -0700 |
| commit | e612dade12b30bdee15b7dd2535af51e5ec1614d (patch) | |
| tree | e38be54476c557471cc8a30bc8c140d7c2797b3a /README.md | |
| parent | 014606affe3f1753ac16d2afd684967d72d83746 (diff) | |
| parent | 477e566e8d203ec7754c90fc845d7f3f759f2974 (diff) | |
| download | yosys-e612dade12b30bdee15b7dd2535af51e5ec1614d.tar.gz yosys-e612dade12b30bdee15b7dd2535af51e5ec1614d.tar.bz2 yosys-e612dade12b30bdee15b7dd2535af51e5ec1614d.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 8 |
1 files changed, 8 insertions, 0 deletions
@@ -350,6 +350,14 @@ Verilog Attributes and non-standard features through the synthesis. When entities are combined, a new |-separated string is created that contains all the string from the original entities. +- The ``defaultvalue`` attribute is used to store default values for + module inputs. The attribute is attached to the input wire by the HDL + front-end when the input is declared with a default value. + +- The ``parameter`` and ``localparam`` attributes are used to mark wires + that represent module parameters or localparams (when the HDL front-end + is run in -pwires mode). + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset |