From 8d0cd529c936b1c0a38d7a71a4457bd84c8b3efe Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 19 Jun 2019 11:37:11 +0200 Subject: Add defaultvalue attribute Signed-off-by: Clifford Wolf --- README.md | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index 94ea9538f..637703a7f 100644 --- a/README.md +++ b/README.md @@ -350,6 +350,10 @@ Verilog Attributes and non-standard features through the synthesis. When entities are combined, a new |-separated string is created that contains all the string from the original entities. +- The ``defaultvalue`` attribute is used to store default values for + module inputs. The attribute is attached to the input wire by the HDL + front-end when the input is declared with a default value. + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset -- cgit v1.2.3 From ec4565009ae69409eb01f1b595f5f59fcc969ce2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 19 Jun 2019 14:38:50 +0200 Subject: Add "read_verilog -pwires" feature, closes #1106 Signed-off-by: Clifford Wolf --- README.md | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index 637703a7f..42f972c8e 100644 --- a/README.md +++ b/README.md @@ -354,6 +354,10 @@ Verilog Attributes and non-standard features module inputs. The attribute is attached to the input wire by the HDL front-end when the input is declared with a default value. +- The ``parameter`` and ``localparam`` attributes are used to mark wires + that represent module parameters or localparams (when the HDL front-end + is run in -pwires mode). + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset -- cgit v1.2.3