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| author | Clifford Wolf <clifford@clifford.at> | 2013-04-07 16:42:29 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-04-07 16:42:29 +0200 |
| commit | 32dbf7752d5ae41966bf19773bf8561b538fe8f0 (patch) | |
| tree | bd388e8adfa4d4ccaef087048e9a1022fc60fe52 /Makefile | |
| parent | af4444e5b96e133f0c64b931759acf5df86475ad (diff) | |
| download | yosys-32dbf7752d5ae41966bf19773bf8561b538fe8f0.tar.gz yosys-32dbf7752d5ae41966bf19773bf8561b538fe8f0.tar.bz2 yosys-32dbf7752d5ae41966bf19773bf8561b538fe8f0.zip | |
Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions