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| author | Clifford Wolf <clifford@clifford.at> | 2019-10-27 10:25:01 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-27 10:25:01 +0100 |
| commit | 81876a3734dacde199446343ce338b24e9b2796f (patch) | |
| tree | f637930db9d29efaeb4609017f07761f012b6d99 /CodingReadme | |
| parent | 84982b308343315c889d3d00116db820a51cad78 (diff) | |
| parent | 4f426c2ac48bbb5ae9e92ca046aa20af35d75a52 (diff) | |
| download | yosys-81876a3734dacde199446343ce338b24e9b2796f.tar.gz yosys-81876a3734dacde199446343ce338b24e9b2796f.tar.bz2 yosys-81876a3734dacde199446343ce338b24e9b2796f.zip | |
Merge pull request #1393 from whitequark/write_verilog-avoid-init
write_verilog: do not print (*init*) attributes on regs
Diffstat (limited to 'CodingReadme')
0 files changed, 0 insertions, 0 deletions