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| author | whitequark <whitequark@whitequark.org> | 2019-09-22 16:52:06 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-09-22 16:52:06 +0000 |
| commit | 4f426c2ac48bbb5ae9e92ca046aa20af35d75a52 (patch) | |
| tree | f3a646aa0fba1dfa89a336cace906a37b75648e8 /CodingReadme | |
| parent | be0eaf3a9abd410d9ea2962a186b104d8ed0cc04 (diff) | |
| download | yosys-4f426c2ac48bbb5ae9e92ca046aa20af35d75a52.tar.gz yosys-4f426c2ac48bbb5ae9e92ca046aa20af35d75a52.tar.bz2 yosys-4f426c2ac48bbb5ae9e92ca046aa20af35d75a52.zip | |
write_verilog: do not print (*init*) attributes on regs.
If an init value is emitted for a reg, an (*init*) attribute is never
necessary, since it is exactly equivalent. On the other hand, some
tools that consume Verilog (ISE, Vivado, Quartus) complain about
(*init*) attributes because their interpretation differs from Yosys.
All (*init*) attributes that would not become reg init values anyway
are emitted as before.
Diffstat (limited to 'CodingReadme')
0 files changed, 0 insertions, 0 deletions