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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:46:52 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:46:52 -0700 |
| commit | 691e145cda416787fe214b5533c6ac3c8047bb65 (patch) | |
| tree | ac78e40defe12c75bcc040f973217ad6875bf5af /CHANGELOG | |
| parent | 7eec64a38fb9362a43916aec79c7fca04b6ba72c (diff) | |
| parent | 8fa74287a71fc3527cf48c7fb2c4a635ee832b72 (diff) | |
| download | yosys-691e145cda416787fe214b5533c6ac3c8047bb65.tar.gz yosys-691e145cda416787fe214b5533c6ac3c8047bb65.tar.bz2 yosys-691e145cda416787fe214b5533c6ac3c8047bb65.zip | |
Merge branch 'xaig' into xc7mux
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 6 |
1 files changed, 4 insertions, 2 deletions
@@ -17,9 +17,11 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "rename -src" - Added "equiv_opt" pass - Added "read_aiger" frontend - - Added "muxpack" pass + - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) + - Added "synth_xilinx -abc9" (experimental) + - Added "synth_ice40 -abc9" (experimental) + - Added "synth -abc9" (experimental) - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" - - "synth_xilinx" to now infer wide multiplexers Yosys 0.7 .. Yosys 0.8 |