From 882a83c383e277e51083019227a88c38bc6b1c68 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 09:04:31 -0700 Subject: Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" This reverts commit eaee250a6e63e58dfef63fa30c4120db78223e24, reversing changes made to 935df3569b4677ac38041ff01a2f67185681f4e3. --- CHANGELOG | 1 - 1 file changed, 1 deletion(-) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index c1b548aeb..28f36b458 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -17,7 +17,6 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "rename -src" - Added "equiv_opt" pass - Added "read_aiger" frontend - - Added "muxpack" pass - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" - "synth_xilinx" to now infer wide multiplexers -- cgit v1.2.3 From 738fdfe8f55e18ac7f315cd68c117eae370004ca Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 09:20:46 -0700 Subject: Remove wide mux inference --- CHANGELOG | 1 - 1 file changed, 1 deletion(-) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 28f36b458..839fefcf1 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -18,7 +18,6 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "equiv_opt" pass - Added "read_aiger" frontend - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" - - "synth_xilinx" to now infer wide multiplexers Yosys 0.7 .. Yosys 0.8 -- cgit v1.2.3 From c04482b07798cfcca3218cfafe0998eeb6a88f76 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 16:54:12 -0700 Subject: Update CHANGELOG --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 839fefcf1..6e3faa9ff 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -17,6 +17,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "rename -src" - Added "equiv_opt" pass - Added "read_aiger" frontend + - Added "abc9" pass (experimental, accessible using synth_xilinx -abc9 and synth_ice40 -abc9) - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" -- cgit v1.2.3 From 9d34cea65af5b34ce0930fb892fca6742db898ab Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Jun 2019 08:22:22 -0700 Subject: More accurate CHANGELOG --- CHANGELOG | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 6e3faa9ff..139f71672 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -17,7 +17,9 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "rename -src" - Added "equiv_opt" pass - Added "read_aiger" frontend - - Added "abc9" pass (experimental, accessible using synth_xilinx -abc9 and synth_ice40 -abc9) + - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) + - Added "synth_xilinx -abc9" (experimental) + - Added "synth_ice40 -abc9" (experimental) - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" -- cgit v1.2.3 From 7f9d2d18251c3bec667993c744b568bbbe1a75ce Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Jun 2019 09:15:30 -0700 Subject: Update CHANGELOG with "synth -abc9" --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 139f71672..44e32c6a8 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -20,6 +20,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) + - Added "synth -abc9" (experimental) - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" -- cgit v1.2.3