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| author | Clifford Wolf <clifford@clifford.at> | 2017-08-28 15:29:58 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-08-28 15:29:58 +0200 |
| commit | a682800187612d8d2ba477be8e2f2021b0b55e9b (patch) | |
| tree | 583f894b080d3cd84d09007e4a70584a1d69c907 | |
| parent | 68c42f3a19a300583fa282f3b88c440bf6afd484 (diff) | |
| parent | e62362225c8a53de1007f6ecc69b58b9bf1fdad9 (diff) | |
| download | yosys-a682800187612d8d2ba477be8e2f2021b0b55e9b.tar.gz yosys-a682800187612d8d2ba477be8e2f2021b0b55e9b.tar.bz2 yosys-a682800187612d8d2ba477be8e2f2021b0b55e9b.zip | |
Merge pull request #392 from azonenberg/greenpak-portfixes
Fixed bug causing GP_SPI model to not synthesize
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 2d7bed5cd..15bbba723 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -113,8 +113,8 @@ module GP_SPI( output reg[7:0] RXD_LOW, output reg INT); - initial DOUT_HIGH = 0; - initial DOUT_LOW = 0; + initial RXD_HIGH = 0; + initial RXD_LOW = 0; initial INT = 0; parameter DATA_WIDTH = 8; //byte or word width |