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| author | Clifford Wolf <clifford@clifford.at> | 2017-08-25 16:18:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-08-25 16:18:17 +0200 |
| commit | 68c42f3a19a300583fa282f3b88c440bf6afd484 (patch) | |
| tree | d318e1fc730947190bc4d1c1f31fe01823a21016 | |
| parent | db6d78a1865456076fccfb44d40fa9a4adecd23b (diff) | |
| download | yosys-68c42f3a19a300583fa282f3b88c440bf6afd484.tar.gz yosys-68c42f3a19a300583fa282f3b88c440bf6afd484.tar.bz2 yosys-68c42f3a19a300583fa282f3b88c440bf6afd484.zip | |
Don't track , ... contradictions through x/z-bits
| -rw-r--r-- | passes/opt/opt_expr.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 08c850a0c..45331aa0b 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1277,7 +1277,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons { SigBit bit_a = i < a_width ? assign_map(sig_a[i]) : State::S0; SigBit bit_b = i < b_width ? assign_map(sig_b[i]) : State::S0; - contradiction_cache.merge(bit_a, bit_b); + + if (bit_a != State::Sx && bit_a != State::Sz && + bit_b != State::Sx && bit_b != State::Sz) + contradiction_cache.merge(bit_a, bit_b); if (bit_b < bit_a) std::swap(bit_a, bit_b); |