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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-05 14:46:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-05 14:46:33 +0200 |
| commit | 238ff1481091a9dd006edd6b68c77b5568639ce9 (patch) | |
| tree | f48795aa6e5867a20b04964dc3ff8ab4180a148b | |
| parent | 45105faf25150a56c6396cc8221be6a9b9c6870e (diff) | |
| download | yosys-238ff1481091a9dd006edd6b68c77b5568639ce9.tar.gz yosys-238ff1481091a9dd006edd6b68c77b5568639ce9.tar.bz2 yosys-238ff1481091a9dd006edd6b68c77b5568639ce9.zip | |
Added CARRY4 Xilinx cell to xsthammer cell lib
| -rw-r--r-- | tests/xsthammer/xl_cells.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/xsthammer/xl_cells.v b/tests/xsthammer/xl_cells.v index 638053fe7..3c1e77d2e 100644 --- a/tests/xsthammer/xl_cells.v +++ b/tests/xsthammer/xl_cells.v @@ -99,3 +99,16 @@ output O; assign O = CI ^ LI; endmodule +module CARRY4(CO, O, CI, CYINIT, DI, S); +output [3:0] CO, O; +input CI, CYINIT; +input [3:0] DI, S; +wire ci_or_cyinit; +assign O = S ^ {CO[2:0], ci_or_cyinit}; +assign CO[0] = S[0] ? ci_or_cyinit : DI[0]; +assign CO[1] = S[1] ? CO[0] : DI[1]; +assign CO[2] = S[2] ? CO[1] : DI[2]; +assign CO[3] = S[3] ? CO[2] : DI[3]; +assign ci_or_cyinit = CI | CYINIT; +endmodule + |