From 238ff1481091a9dd006edd6b68c77b5568639ce9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 5 Jul 2013 14:46:33 +0200 Subject: Added CARRY4 Xilinx cell to xsthammer cell lib --- tests/xsthammer/xl_cells.v | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tests/xsthammer/xl_cells.v b/tests/xsthammer/xl_cells.v index 638053fe7..3c1e77d2e 100644 --- a/tests/xsthammer/xl_cells.v +++ b/tests/xsthammer/xl_cells.v @@ -99,3 +99,16 @@ output O; assign O = CI ^ LI; endmodule +module CARRY4(CO, O, CI, CYINIT, DI, S); +output [3:0] CO, O; +input CI, CYINIT; +input [3:0] DI, S; +wire ci_or_cyinit; +assign O = S ^ {CO[2:0], ci_or_cyinit}; +assign CO[0] = S[0] ? ci_or_cyinit : DI[0]; +assign CO[1] = S[1] ? CO[0] : DI[1]; +assign CO[2] = S[2] ? CO[1] : DI[2]; +assign CO[3] = S[3] ? CO[2] : DI[3]; +assign ci_or_cyinit = CI | CYINIT; +endmodule + -- cgit v1.2.3