| Commit message (Expand) | Author | Age | Files | Lines |
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| * | ice40: raise CE global promotion threshold. | whitequark | 2018-11-29 | 1 | -1/+1 |
| * | Merge pull request #155 from smunaut/issue_151 | David Shah | 2018-11-28 | 1 | -48/+48 |
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| | * | ice40: Update the way LVDS inputs are handled during bitstream generation | Sylvain Munaut | 2018-11-28 | 1 | -48/+48 |
| * | | ice40: Try to be helpful and suggest using PAD PLL instead of CORE | Sylvain Munaut | 2018-11-28 | 1 | -2/+14 |
| * | | ice40: Revamp the whole PLL placement/validity check logic | Sylvain Munaut | 2018-11-28 | 1 | -72/+200 |
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| * | ice40: Finer-grained control of global promotion | David Shah | 2018-11-27 | 2 | -3/+14 |
| * | ice40: During global promotion, only promote if this will actually fit ! | Sylvain Munaut | 2018-11-26 | 1 | -6/+32 |
| * | ice40: Add helper to know which global network is driven by a SB_GB Bel | Sylvain Munaut | 2018-11-26 | 2 | -2/+8 |
| * | ice40: Improve PCF error handling | David Shah | 2018-11-26 | 1 | -3/+9 |
| * | Merge branch 'master' of github.com:YosysHQ/nextpnr | David Shah | 2018-11-26 | 1 | -0/+2 |
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| | * | ice40: Fix disconnection of PACKAGEPIN for PAD PLLs | David Shah | 2018-11-24 | 1 | -0/+2 |
| * | | python: Fixes to get net wires map working | David Shah | 2018-11-22 | 1 | -2/+24 |
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| * | ice40/pll: Fix typo when testing for global port output net | Sylvain Munaut | 2018-11-20 | 1 | -1/+1 |
| * | ice40: Add support for SB_RGBA_DRV | Sylvain Munaut | 2018-11-19 | 5 | -2/+58 |
| * | ice40: Add global network output support for LFOSC/HFOSC | Sylvain Munaut | 2018-11-19 | 1 | -2/+10 |
| * | ice40/pack: Add helper to constain cells that are unique in the FPGA | Sylvain Munaut | 2018-11-19 | 1 | -0/+16 |
| * | ice40: Add support for SB_GB_IO | Sylvain Munaut | 2018-11-19 | 5 | -8/+31 |
| * | ice40: Add support for PLL global outputs via PADIN | Sylvain Munaut | 2018-11-19 | 2 | -84/+73 |
| * | ice40: Introduce the concept of forPadIn SB_GB | Sylvain Munaut | 2018-11-19 | 5 | -2/+53 |
| * | ice40/chipdb: Add wires to global network for all cells that can drive it | Sylvain Munaut | 2018-11-19 | 3 | -6/+22 |
| * | ice40: Add GlobalNetowkrInfo in the chip database | Sylvain Munaut | 2018-11-19 | 2 | -37/+63 |
| * | ice40: Fix BEL validity check for PLL vs SB_IO | Sylvain Munaut | 2018-11-19 | 1 | -21/+20 |
| * | ice40: Improve the is_sb_pll40_XXX predicates collection | Sylvain Munaut | 2018-11-19 | 1 | -1/+13 |
| * | ice40: Fix PLLTYPE for SB_PLL40_2F_PAD | Sylvain Munaut | 2018-11-19 | 1 | -1/+1 |
| * | ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributes | Sylvain Munaut | 2018-11-19 | 1 | -0/+18 |
| * | ice40: Make PLL default FEEDBACK_MODE to SIMPLE | Sylvain Munaut | 2018-11-19 | 1 | -1/+1 |
| * | ice40: Minor fix in predicate checking for logic port | Sylvain Munaut | 2018-11-19 | 1 | -2/+3 |
| * | ice40/pack: Stop looking for BEL when we have one during PLL placement | Sylvain Munaut | 2018-11-19 | 1 | -0/+1 |
| * | ice40/pack: Allow PLL to be constrained via 'BEL' attributes | Sylvain Munaut | 2018-11-19 | 1 | -0/+10 |
| * | ice40/pack: Make sure we don't use a LOCKED bel when placing PLL | Sylvain Munaut | 2018-11-19 | 1 | -0/+2 |
| * | ice40/arch: Add helper to check if a BEL is LOCKED or not | Sylvain Munaut | 2018-11-19 | 2 | -0/+21 |
| * | ice40/chipdb: Fix LOCKED keyword support to include all packages | Sylvain Munaut | 2018-11-19 | 1 | -1/+2 |
| * | ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IO | Sylvain Munaut | 2018-11-19 | 1 | -2/+7 |
| * | ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere | Sylvain Munaut | 2018-11-16 | 1 | -0/+5 |
| * | ice40/bitstream: Convert to UNIX line endings | Sylvain Munaut | 2018-11-16 | 1 | -1043/+1043 |
| * | clangformat | David Shah | 2018-11-16 | 1 | -2/+2 |
| * | ice40: Remove unnecessary RAM assertion | David Shah | 2018-11-16 | 1 | -1/+0 |
| * | Merge remote-tracking branch 'origin/master' into timingapi | Eddie Hung | 2018-11-13 | 2 | -4/+5 |
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| | * | [ice40] getBudgetOverride() to use constrained Z not placed Z | Eddie Hung | 2018-11-13 | 2 | -4/+5 |
| * | | Merge remote-tracking branch 'origin/master' into timingapi | Eddie Hung | 2018-11-13 | 3 | -18/+41 |
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| | * | Merge pull request #107 from YosysHQ/router_improve | Eddie Hung | 2018-11-13 | 2 | -17/+40 |
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| | | * | Various router1 fixes, Add BelId/WireId/PipId::operator<() | Clifford Wolf | 2018-11-13 | 1 | -0/+3 |
| | | * | clangformat | Clifford Wolf | 2018-11-11 | 1 | -4/+1 |
| | | * | Add getConflictingWireWire() arch API, streamline getConflictingXY semantic | Clifford Wolf | 2018-11-11 | 1 | -14/+29 |
| | | * | Add getConflictingPipWire() arch API, router1 improvements | Clifford Wolf | 2018-11-11 | 1 | -9/+17 |
| | * | | Mark getArchOptions as override in derived classes | Pedro Vanzella | 2018-11-13 | 1 | -1/+1 |
| * | | | timing: Add support for clock constraints | David Shah | 2018-11-12 | 2 | -0/+12 |
| * | | | archapi: Add getDelayFromNS to improve timing algorithm portability | David Shah | 2018-11-12 | 1 | -0/+6 |
| * | | | timing: Fix handling of clock inputs | David Shah | 2018-11-12 | 1 | -2/+2 |
| * | | | Working on multi-clock analysis | David Shah | 2018-11-12 | 1 | -6/+4 |
