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| author | David Shah <dave@ds0.me> | 2018-11-03 14:09:27 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2018-11-12 14:03:58 +0000 |
| commit | e633aa09ccd89040d450b7cb4b7864c4fd8c0468 (patch) | |
| tree | f7d2a04e90cf25a0f836d72485114f8e76f056b6 /ice40 | |
| parent | fad69d49309ec979f0251a3213f212968629a8ed (diff) | |
| download | nextpnr-e633aa09ccd89040d450b7cb4b7864c4fd8c0468.tar.gz nextpnr-e633aa09ccd89040d450b7cb4b7864c4fd8c0468.tar.bz2 nextpnr-e633aa09ccd89040d450b7cb4b7864c4fd8c0468.zip | |
timing: Fix handling of clock inputs
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'ice40')
| -rw-r--r-- | ice40/arch.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc index c14fecc4..2d910d6f 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -894,7 +894,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in else return TMG_REGISTER_INPUT; } else if (cell->type == id_ICESTORM_DSP || cell->type == id_ICESTORM_SPRAM) { - if (port == id_CLK) + if (port == id_CLK || port == id_CLOCK) return TMG_CLOCK_INPUT; else { clockInfoCount = 1; @@ -960,7 +960,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.hold.delay = 0; } } else if (cell->type == id_ICESTORM_DSP || cell->type == id_ICESTORM_SPRAM) { - info.clock_port = id_CLK; + info.clock_port = cell->type == id_ICESTORM_SPRAM ? id_CLOCK : id_CLK; info.edge = RISING_EDGE; if (cell->ports.at(port).type == PORT_OUT) { bool has_clktoq = getCellDelay(cell, info.clock_port, port, info.clockToQ); |