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* Towards IdString as per-context facilityClifford Wolf2018-06-181-2/+2
* Rename chip.h to arch.hClifford Wolf2018-06-182-1/+1
* Updates from clangformatClifford Wolf2018-06-183-6/+4
* Rename Design to Context, derive from Arch instead of instantiatingClifford Wolf2018-06-1811-130/+126
* Rename Chip to Arch and ChipArgs to ArchArgsClifford Wolf2018-06-186-104/+105
* Fix hash specialisation for BelType and warnings in place_sa.ccDavid Shah2018-06-181-0/+11
* Improving code style and fixing dummyDavid Shah2018-06-181-1/+2
* Updates from clangformatClifford Wolf2018-06-171-5/+10
* Refactore ice40 chipdb to use a super-large C-string as output formatClifford Wolf2018-06-173-27/+85
* Minor chipdb.py improvementClifford Wolf2018-06-171-2/+17
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into chipdbngClifford Wolf2018-06-174-28/+56
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| * Minor performance tweaks and fixesDavid Shah2018-06-171-21/+27
| * ice40: Fixing negative clock bitstream generationDavid Shah2018-06-171-1/+8
| * place_sa: Adding seed optionDavid Shah2018-06-172-2/+12
| * place_sa: Add a rip-up feature when initial placement failsDavid Shah2018-06-172-6/+11
* | Updates from clangformatClifford Wolf2018-06-172-22/+25
* | Move top-level ChipInfoPOD into ice40 chipdb blobClifford Wolf2018-06-174-126/+139
* | Move PackageInfoPOD to ice40 chipdb blobClifford Wolf2018-06-173-10/+12
* | Move TileType array to ice40 chipdb blobClifford Wolf2018-06-172-7/+14
* | Move BitstreamInfoPOD to ice40 chipdb blobClifford Wolf2018-06-173-17/+23
* | Move IerenInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-12/+11
* | Move TileInfoPOD to chipdb blobClifford Wolf2018-06-172-8/+16
* | Move SwitchInfoPOD to chipdb blobClifford Wolf2018-06-172-15/+25
* | Move PipInfoPOD into ChipDB binary blobClifford Wolf2018-06-171-6/+28
* | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into chipdbngClifford Wolf2018-06-1712-53/+200
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| * General reformattingDavid Shah2018-06-173-3/+3
| * ice40: Add symbol output to bitstream generationDavid Shah2018-06-171-6/+8
| * Updating copyrightsDavid Shah2018-06-1711-4/+12
| * Improving the placer outputDavid Shah2018-06-172-1/+4
| * Add 'get or default' functionsDavid Shah2018-06-171-3/+4
| * ice40: Fixing buildDavid Shah2018-06-172-2/+2
| * place: Fix placer validity checksDavid Shah2018-06-162-0/+24
| * ice40: Proper global promotionDavid Shah2018-06-164-24/+83
| * ice40: Promote reset signalDavid Shah2018-06-164-32/+82
* | Move WireInfoPOD into ChipDB binary blobClifford Wolf2018-06-173-39/+61
* | Minor refactoring of BinaryBlobAssembler, fix alignmentsClifford Wolf2018-06-174-84/+145
* | Progress with chipdb refactoringClifford Wolf2018-06-164-23/+39
* | Progress with chipdb refactoringClifford Wolf2018-06-163-42/+37
* | Progress with chipdb refactoringClifford Wolf2018-06-163-33/+175
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* Update clangformatClifford Wolf2018-06-161-1/+1
* Merge remote-tracking branch 'origin/master' into chipdbngClifford Wolf2018-06-168-21/+122
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| * ice40: Fix RAM config in packerDavid Shah2018-06-161-1/+2
| * ice40: Fix BRAM initialisationDavid Shah2018-06-162-4/+4
| * place: Tidying up the SA placerDavid Shah2018-06-161-1/+1
| * ice40: Include RAM init data in bitstreamDavid Shah2018-06-161-0/+40
| * ice40: Fix bitstream generation when parameters are unspecifiedDavid Shah2018-06-161-13/+23
| * ice40: Bitstream generation for RAMDavid Shah2018-06-161-1/+36
| * ice40: Only place IO at valid pinsDavid Shah2018-06-163-3/+14
| * experiment: Simple heuristic-based placerDavid Shah2018-06-164-6/+10
* | Some refactoring of Chip API (prep for chipdb refactoring)Clifford Wolf2018-06-163-25/+47
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generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 07:33:07 +0000
="p">(cstart != std::string::npos) line = line.substr(0, cstart); cstart = line.find("//"); if (cstart != std::string::npos) line = line.substr(0, cstart); if (isempty(line)) continue; linebuf += line; // Look for a command up to a semicolon size_t scpos = linebuf.find(';'); while (scpos != std::string::npos) { std::string command = linebuf.substr(0, scpos); // Split command into words std::stringstream ss(command); std::vector<std::string> words; std::string tmp; while (ss >> tmp) words.push_back(tmp); if (words.size() >= 0) { std::string verb = words.at(0); if (verb == "BLOCK") { if (words.size() != 2 || (words.at(1) != "ASYNCPATHS" && words.at(1) != "RESETPATHS")) log_warning(" ignoring unsupported LPF command '%s' (on line %d)\n", command.c_str(), lineno); } else if (verb == "SYSCONFIG") { for (size_t i = 1; i < words.size(); i++) { std::string setting = words.at(i); size_t eqpos = setting.find('='); if (eqpos == std::string::npos) log_error("expected syntax 'SYSCONFIG <attr>=<value>...' (on line %d)\n", lineno); std::string key = setting.substr(0, eqpos), value = setting.substr(eqpos + 1); if (!sysconfig_keys.count(key)) log_error("unexpected SYSCONFIG key '%s' (on line %d)\n", key.c_str(), lineno); settings[id("arch.sysconfig." + key)] = value; } } else if (verb == "FREQUENCY") { if (words.size() < 2) log_error("expected object type after FREQUENCY (on line %d)\n", lineno); std::string etype = words.at(1); if (etype == "PORT" || etype == "NET") { if (words.size() < 4) log_error("expected frequency value and unit after 'FREQUENCY %s' (on line %d)\n", etype.c_str(), lineno); std::string target = strip_quotes(words.at(2)); float freq = std::stof(words.at(3)); std::string unit = words.at(4); boost::algorithm::to_upper(unit); if (unit == "MHZ") ; else if (unit == "KHZ") freq /= 1.0e3; else if (unit == "HZ") freq /= 1.0e6; else log_error("unsupported frequency unit '%s' (on line %d)\n", unit.c_str(), lineno); addClock(id(target), freq); } else { log_warning(" ignoring unsupported LPF command '%s %s' (on line %d)\n", command.c_str(), etype.c_str(), lineno); } } else if (verb == "LOCATE") { if (words.size() < 5) log_error("expected syntax 'LOCATE COMP <port name> SITE <pin>' (on line %d)\n", lineno); if (words.at(1) != "COMP") log_error("expected 'COMP' after 'LOCATE' (on line %d)\n", lineno); std::string cell = strip_quotes(words.at(2)); if (words.at(3) != "SITE") log_error("expected 'SITE' after 'LOCATE COMP %s' (on line %d)\n", cell.c_str(), lineno); auto fnd_cell = cells.find(id(cell)); if (words.size() > 5) log_error("unexpected input following LOCATE clause (on line %d)\n", lineno); if (fnd_cell != cells.end()) { fnd_cell->second->attrs[id("LOC")] = strip_quotes(words.at(4)); } } else if (verb == "IOBUF") { if (words.size() < 3) log_error("expected syntax 'IOBUF PORT <port name> <attr>=<value>...' (on line %d)\n", lineno); if (words.at(1) != "PORT") log_error("expected 'PORT' after 'IOBUF' (on line %d)\n", lineno); std::string cell = strip_quotes(words.at(2)); auto fnd_cell = cells.find(id(cell)); if (fnd_cell != cells.end()) { for (size_t i = 3; i < words.size(); i++) { std::string setting = words.at(i); size_t eqpos = setting.find('='); if (eqpos == std::string::npos) log_error( "expected syntax 'IOBUF PORT <port name> <attr>=<value>...' (on line %d)\n", lineno); std::string key = setting.substr(0, eqpos), value = setting.substr(eqpos + 1); if (!iobuf_keys.count(key)) log_warning("IOBUF '%s' attribute '%s' is not recognised (on line %d)\n", cell.c_str(), key.c_str(), lineno); fnd_cell->second->attrs[id(key)] = value; } } } } linebuf = linebuf.substr(scpos + 1); scpos = linebuf.find(';'); } } if (!isempty(linebuf)) log_error("unexpected end of LPF file\n"); settings[id("input/lpf")] = filename; return true; } catch (log_execution_error_exception) { return false; } } NEXTPNR_NAMESPACE_END