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author | David Shah <davey1576@gmail.com> | 2018-06-17 15:21:35 +0200 |
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committer | David Shah <davey1576@gmail.com> | 2018-06-17 15:21:35 +0200 |
commit | f723aaa373e188a4c926eff07c4c63b0d8467e0e (patch) | |
tree | f7456afb3e58471cdbff673e9851f3f4cffb0c36 /ice40 | |
parent | 748171dae29c65182e6360a12a9e2bdbbfc35163 (diff) | |
download | nextpnr-f723aaa373e188a4c926eff07c4c63b0d8467e0e.tar.gz nextpnr-f723aaa373e188a4c926eff07c4c63b0d8467e0e.tar.bz2 nextpnr-f723aaa373e188a4c926eff07c4c63b0d8467e0e.zip |
ice40: Fixing negative clock bitstream generation
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ice40')
-rw-r--r-- | ice40/bitstream.cc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 9309a7da..23cd6af1 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -19,6 +19,7 @@ */ #include "bitstream.h" #include <vector> +#include "log.h" NEXTPNR_NAMESPACE_BEGIN @@ -59,11 +60,16 @@ void set_config(const TileInfoPOD &ti, if (index == -1) { for (int i = 0; i < cfg.num_bits; i++) { int8_t &cbit = tile_cfg.at(cfg.bits[i].row).at(cfg.bits[i].col); + if (cbit && !value) + log_error("clearing already set config bit %s", name.c_str()); cbit = value; } } else { int8_t &cbit = tile_cfg.at(cfg.bits[index].row).at(cfg.bits[index].col); cbit = value; + if (cbit && !value) + log_error("clearing already set config bit %s[%d]", name.c_str(), + index); } } @@ -179,7 +185,8 @@ void write_asc(const Design &design, std::ostream &out) for (int i = 0; i < 20; i++) set_config(ti, config.at(y).at(x), "LC_" + std::to_string(z), lc.at(i), i); - set_config(ti, config.at(y).at(x), "NegClk", neg_clk); + if (dff_enable) + set_config(ti, config.at(y).at(x), "NegClk", neg_clk); } else if (cell.second->type == "SB_IO") { TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; unsigned pin_type = get_param_or_def(cell.second, "PIN_TYPE"); |