Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into chipdbng

12 files changed, 200 insertions, 53 deletions

diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index 492ed846..1c6361a1 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -2,6 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -19,6 +20,7 @@
 
 #include "arch_place.h"
 #include "cells.h"
+#include "util.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
@@ -39,7 +41,7 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
     std::unordered_set<const NetInfo *> locals;
 
     for (auto cell : cells) {
-        if (std::stoi(cell->params.at("DFF_ENABLE"))) {
+        if (bool_or_default(cell->params, "DFF_ENABLE")) {
             if (!dffs_exist) {
                 dffs_exist = true;
                 cen = get_net_or_nullptr(cell, "CEN");
@@ -53,7 +55,7 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
                 if (!is_global_net(sr))
                     locals.insert(sr);
 
-                if (std::stoi(cell->params.at("NEG_CLK"))) {
+                if (bool_or_default(cell->params, "NEG_CLK")) {
                     dffs_neg = true;
                 }
             } else {
@@ -63,7 +65,7 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
                     return false;
                 if (sr != get_net_or_nullptr(cell, "SR"))
                     return false;
-                if (dffs_neg != bool(std::stoi(cell->params.at("NEG_CLK"))))
+                if (dffs_neg != bool_or_default(cell->params, "NEG_CLK"))
                     return false;
             }
         }
@@ -79,6 +81,28 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
     return locals.size() <= 32;
 }
 
+bool isBelLocationValid(Design *design, BelId bel)
+{
+    const Chip &chip = design->chip;
+    if (chip.getBelType(bel) == TYPE_ICESTORM_LC) {
+        std::vector<const CellInfo *> cells;
+        for (auto bel_other : chip.getBelsAtSameTile(bel)) {
+            IdString cell_other = chip.getBelCell(bel_other, false);
+            if (cell_other != IdString()) {
+                const CellInfo *ci_other = design->cells[cell_other];
+                cells.push_back(ci_other);
+            }
+        }
+        return logicCellsCompatible(cells);
+    } else {
+        IdString cellId = chip.getBelCell(bel, false);
+        if (cellId == IdString())
+            return true;
+        else
+            return isValidBelForCell(design, design->cells.at(cellId), bel);
+    }
+}
+
 bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel)
 {
     const Chip &chip = design->chip;
@@ -99,6 +123,26 @@ bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel)
         return logicCellsCompatible(cells);
     } else if (cell->type == "SB_IO") {
         return design->chip.getBelPackagePin(bel) != "";
+    } else if (cell->type == "SB_GB") {
+        bool is_reset = false, is_cen = false;
+        assert(cell->ports.at("GLOBAL_BUFFER_OUTPUT").net != nullptr);
+        for (auto user : cell->ports.at("GLOBAL_BUFFER_OUTPUT").net->users) {
+            if (is_reset_port(user))
+                is_reset = true;
+            if (is_enable_port(user))
+                is_cen = true;
+        }
+        IdString glb_net = chip.getWireName(
+                chip.getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT));
+        int glb_id = std::stoi(std::string("") + glb_net.str().back());
+        if (is_reset && is_cen)
+            return false;
+        else if (is_reset)
+            return (glb_id % 2) == 0;
+        else if (is_cen)
+            return (glb_id % 2) == 1;
+        else
+            return true;
     } else {
         // TODO: IO cell clock checks
         return true;
diff --git a/ice40/arch_place.h b/ice40/arch_place.h
index a505f4db..5cd14809 100644
--- a/ice40/arch_place.h
+++ b/ice40/arch_place.h
@@ -2,6 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -12,7 +13,7 @@
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  ACTION OF CONTRACT, NeEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
@@ -30,6 +31,9 @@ NEXTPNR_NAMESPACE_BEGIN
 // such as conflicting set/reset signals, etc
 bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel);
 
+// Return true whether all Bels at a given location are valid
+bool isBelLocationValid(Design *design, BelId bel);
+
 NEXTPNR_NAMESPACE_END
 
 #endif
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 61a6959d..2913303c 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -2,7 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@clifford.at>
- *  Copyright (C) 2018  David Shah <dave@ds0.me>
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -287,12 +287,6 @@ void write_asc(const Design &design, std::ostream &out)
             TileType tile = tile_at(chip, x, y);
             TileInfoPOD &ti = bi.tiles_nonrouting[tile];
 
-            // disable RAM to stop icebox_vlog crashing (FIXME)
-            if ((tile == TILE_RAMB) && (chip.args.type == ChipArgs::LP1K ||
-                                        chip.args.type == ChipArgs::HX1K)) {
-                set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true);
-            }
-
             // set all ColBufCtrl bits (FIXME)
             bool setColBufCtrl = true;
             if (chip.args.type == ChipArgs::LP1K ||
@@ -398,6 +392,14 @@ void write_asc(const Design &design, std::ostream &out)
             }
         }
     }
+
+    // Write symbols
+    const bool write_symbols = 1;
+    for (auto wire : chip.getWires()) {
+        IdString net = chip.getWireNet(wire, false);
+        if (net != IdString())
+            out << ".sym " << wire.index << " " << net << std::endl;
+    }
 }
 
 NEXTPNR_NAMESPACE_END
diff --git a/ice40/bitstream.h b/ice40/bitstream.h
index 11547163..0e2a4aa9 100644
--- a/ice40/bitstream.h
+++ b/ice40/bitstream.h
@@ -2,6 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
diff --git a/ice40/cells.cc b/ice40/cells.cc
index 61b24ce3..b11a2a77 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -2,6 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -190,6 +191,41 @@ void nxio_to_sb(CellInfo *nxio, CellInfo *sbio)
     }
 }
 
+bool is_clock_port(const PortRef &port)
+{
+    if (port.cell == nullptr)
+        return false;
+    if (is_ff(port.cell))
+        return port.port == "C";
+    if (port.cell->type == "ICESTORM_LC")
+        return port.port == "CLK";
+    if (is_ram(port.cell) || port.cell->type == "ICESTORM_RAM")
+        return port.port == "RCLK" || port.port == "WCLK";
+    return false;
+}
+
+bool is_reset_port(const PortRef &port)
+{
+    if (port.cell == nullptr)
+        return false;
+    if (is_ff(port.cell))
+        return port.port == "R" || port.port == "S";
+    if (port.cell->type == "ICESTORM_LC")
+        return port.port == "SR";
+    return false;
+}
+
+bool is_enable_port(const PortRef &port)
+{
+    if (port.cell == nullptr)
+        return false;
+    if (is_ff(port.cell))
+        return port.port == "E";
+    if (port.cell->type == "ICESTORM_LC")
+        return port.port == "CEN";
+    return false;
+}
+
 bool is_global_net(const NetInfo *net)
 {
     return bool(net_driven_by(net, is_gbuf, "GLOBAL_BUFFER_OUTPUT"));
diff --git a/ice40/cells.h b/ice40/cells.h
index a2fa4c16..45e81fd1 100644
--- a/ice40/cells.h
+++ b/ice40/cells.h
@@ -2,6 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -77,6 +78,15 @@ void nxio_to_sb(CellInfo *nxio, CellInfo *sbio);
 // Return true if a net is a global net
 bool is_global_net(const NetInfo *net);
 
+// Return true if a port is a clock port
+bool is_clock_port(const PortRef &port);
+
+// Return true if a port is a reset port
+bool is_reset_port(const PortRef &port);
+
+// Return true if a port is a clock enable port
+bool is_enable_port(const PortRef &port);
+
 NEXTPNR_NAMESPACE_END
 
 #endif
diff --git a/ice40/main.cc b/ice40/main.cc
index fea53631..eb92d92f 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -25,13 +25,14 @@
 #include <fstream>
 #include <iostream>
 #include "bitstream.h"
+#include "design_utils.h"
 #include "jsonparse.h"
 #include "log.h"
 #include "mainwindow.h"
 #include "nextpnr.h"
 #include "pack.h"
 #include "pcf.h"
-#include "place.h"
+#include "place_sa.h"
 #include "pybindings.h"
 #include "route.h"
 #include "version.h"
@@ -221,6 +222,7 @@ int main(int argc, char *argv[])
         }
 
         pack_design(&design);
+        print_utilisation(&design);
         if (!vm.count("pack-only")) {
             place_design_sa(&design);
             route_design(&design, verbose);
diff --git a/ice40/pack.cc b/ice40/pack.cc
index e045c05c..0b76f3f3 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -2,7 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@clifford.at>
- *  Copyright (C) 2018  David Shah <dave@ds0.me>
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -276,15 +276,36 @@ static void pack_io(Design *design)
     }
 }
 
-static bool is_clock_port(const PortRef &port)
+static void insert_global(Design *design, NetInfo *net, bool is_reset,
+                          bool is_cen)
 {
-    if (port.cell == nullptr)
-        return false;
-    if (is_ff(port.cell))
-        return port.port == "C";
-    if (is_ram(port.cell))
-        return port.port == "RCLK" || port.port == "WCLK";
-    return false;
+    CellInfo *gb = create_ice_cell(design, "SB_GB");
+    gb->ports["USER_SIGNAL_TO_GLOBAL_BUFFER"].net = net;
+    PortRef pr;
+    pr.cell = gb;
+    pr.port = "USER_SIGNAL_TO_GLOBAL_BUFFER";
+    net->users.push_back(pr);
+
+    pr.cell = gb;
+    pr.port = "GLOBAL_BUFFER_OUTPUT";
+    NetInfo *glbnet = new NetInfo();
+    glbnet->name = net->name.str() + std::string("_glb_") +
+                   (is_reset ? "sr" : (is_cen ? "ce" : "clk"));
+    glbnet->driver = pr;
+    design->nets[glbnet->name] = glbnet;
+    gb->ports["GLOBAL_BUFFER_OUTPUT"].net = glbnet;
+    std::vector<PortRef> keep_users;
+    for (auto user : net->users) {
+        if (is_clock_port(user) || (is_reset && is_reset_port(user)) ||
+            (is_cen && is_enable_port(user))) {
+            user.cell->ports[user.port].net = glbnet;
+            glbnet->users.push_back(user);
+        } else {
+            keep_users.push_back(user);
+        }
+    }
+    net->users = keep_users;
+    design->cells[gb->name] = gb;
 }
 
 // Simple global promoter (clock only)
@@ -292,48 +313,72 @@ static void promote_globals(Design *design)
 {
     log_info("Promoting globals..\n");
 
-    std::unordered_map<IdString, int> clock_count;
+    std::unordered_map<IdString, int> clock_count, reset_count, cen_count;
     for (auto net : design->nets) {
         NetInfo *ni = net.second;
         if (ni->driver.cell != nullptr && !is_global_net(ni)) {
             clock_count[net.first] = 0;
+            reset_count[net.first] = 0;
+            cen_count[net.first] = 0;
+
             for (auto user : ni->users) {
                 if (is_clock_port(user))
                     clock_count[net.first]++;
+                if (is_reset_port(user))
+                    reset_count[net.first]++;
+                if (is_enable_port(user))
+                    cen_count[net.first]++;
             }
         }
     }
-    auto global_clock = std::max_element(clock_count.begin(), clock_count.end(),
-                                         [](const std::pair<IdString, int> &a,
-                                            const std::pair<IdString, int> &b) {
-                                             return a.second < b.second;
-                                         });
-    if (global_clock->second > 0) {
-        NetInfo *clknet = design->nets[global_clock->first];
-        CellInfo *gb = create_ice_cell(design, "SB_GB");
-        gb->ports["USER_SIGNAL_TO_GLOBAL_BUFFER"].net = clknet;
-        PortRef pr;
-        pr.cell = gb;
-        pr.port = "USER_SIGNAL_TO_GLOBAL_BUFFER";
-        clknet->users.push_back(pr);
-
-        pr.cell = gb;
-        pr.port = "GLOBAL_BUFFER_OUTPUT";
-        NetInfo *glbnet = new NetInfo();
-        glbnet->name = clknet->name.str() + "_glb";
-        glbnet->driver = pr;
-        design->nets[glbnet->name] = glbnet;
-        std::vector<PortRef> keep_users;
-        for (auto user : clknet->users) {
-            if (is_clock_port(user)) {
-                user.cell->ports[user.port].net = glbnet;
-                glbnet->users.push_back(user);
-            } else {
-                keep_users.push_back(user);
-            }
+    int prom_globals = 0, prom_resets = 0, prom_cens = 0;
+    int gbs_available = 8;
+    for (auto cell : design->cells)
+        if (is_gbuf(cell.second))
+            --gbs_available;
+    while (prom_globals < gbs_available) {
+        auto global_clock =
+                std::max_element(clock_count.begin(), clock_count.end(),
+                                 [](const std::pair<IdString, int> &a,
+                                    const std::pair<IdString, int> &b) {
+                                     return a.second < b.second;
+                                 });
+
+        auto global_reset =
+                std::max_element(reset_count.begin(), reset_count.end(),
+                                 [](const std::pair<IdString, int> &a,
+                                    const std::pair<IdString, int> &b) {
+                                     return a.second < b.second;
+                                 });
+        auto global_cen =
+                std::max_element(cen_count.begin(), cen_count.end(),
+                                 [](const std::pair<IdString, int> &a,
+                                    const std::pair<IdString, int> &b) {
+                                     return a.second < b.second;
+                                 });
+        if (global_reset->second > global_clock->second && prom_resets < 4) {
+            NetInfo *rstnet = design->nets[global_reset->first];
+            insert_global(design, rstnet, true, false);
+            ++prom_globals;
+            ++prom_resets;
+            clock_count.erase(rstnet->name);
+            reset_count.erase(rstnet->name);
+
+        } else if (global_cen->second > global_clock->second && prom_cens < 4) {
+            NetInfo *cennet = design->nets[global_cen->first];
+            insert_global(design, cennet, false, true);
+            ++prom_globals;
+            ++prom_cens;
+            cen_count.erase(cennet->name);
+            clock_count.erase(cennet->name);
+        } else if (global_clock->second != 0) {
+            NetInfo *clknet = design->nets[global_clock->first];
+            insert_global(design, clknet, false, false);
+            ++prom_globals;
+            clock_count.erase(clknet->name);
+        } else {
+            break;
         }
-        clknet->users = keep_users;
-        design->cells[gb->name] = gb;
     }
 }
 
diff --git a/ice40/pack.h b/ice40/pack.h
index 4a92a7ab..60f22ef3 100644
--- a/ice40/pack.h
+++ b/ice40/pack.h
@@ -2,6 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
diff --git a/ice40/pcf.cc b/ice40/pcf.cc
index 75c32731..3bef962f 100644
--- a/ice40/pcf.cc
+++ b/ice40/pcf.cc
@@ -2,6 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
diff --git a/ice40/pcf.h b/ice40/pcf.h
index c4a7d991..ec2f4923 100644
--- a/ice40/pcf.h
+++ b/ice40/pcf.h
@@ -2,6 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
diff --git a/ice40/pybindings.cc b/ice40/pybindings.cc
index 5ccf9495..c161949b 100644
--- a/ice40/pybindings.cc
+++ b/ice40/pybindings.cc
@@ -2,7 +2,7 @@
  *  nextpnr -- Next Generation Place and Route
  *
  *  Copyright (C) 2018  Clifford Wolf <clifford@clifford.at>
- *  Copyright (C) 2018  David Shah <dave@ds0.me>
+ *  Copyright (C) 2018  David Shah <david@symbioticeda.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above