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* clang-format for design and chip codebaseClifford Wolf2018-06-072-813/+817
* Fix clang-format include order issuesClifford Wolf2018-06-071-0/+2
* Add ICE40_HX1K_ONLY config macroClifford Wolf2018-06-072-8/+43
* Rename --file to --runClifford Wolf2018-06-071-3/+3
* Allow specifying multiple Python files on the command lineDavid Shah2018-06-071-3/+4
* Allow loading and running Python files before GUI startsDavid Shah2018-06-071-14/+15
* Attempt to add JSON parser--not working yet w/ build systemZipCPU2018-06-061-12/+26
* Add iCE40 device selection, improve iCE40 IO GraphicElementsClifford Wolf2018-06-062-13/+61
* Add simple SVG generator to ice40 mainClifford Wolf2018-06-061-4/+36
* Add ice40 geometry informationClifford Wolf2018-06-063-15/+95
* Add ice40 --test modeClifford Wolf2018-06-062-5/+66
* Refactor Chip API and iCE40 databaseClifford Wolf2018-06-064-166/+376
* Initial GUI workMiodrag Milanovic2018-06-051-7/+75
* Initial JSON parserZipCPU2018-06-051-0/+3
* Add iCE40 blockram belsClifford Wolf2018-06-043-0/+285
* Replace GuiLine with GraphicElementClifford Wolf2018-06-041-7/+4
* Add iCE40 SB_IO belsClifford Wolf2018-06-033-26/+106
* Add ice40 ICESTORM_LC belsClifford Wolf2018-06-023-12/+157
* Remove now obsolete ice40/makefile.incClifford Wolf2018-06-021-17/+0
* Fix race condition and optimise the buildDavid Shah2018-06-022-2/+7
* Python bindings working on both architecturesDavid Shah2018-06-021-9/+2
* Simple Python test workingDavid Shah2018-06-021-0/+37
* Add architecture specific Python defsDavid Shah2018-06-021-0/+27
* Add a CMake based build systemDavid Shah2018-06-021-0/+14
* Use singular in type names (BelRange, WireIterator)Clifford Wolf2018-06-021-18/+18
* Add iCE40 blinky exampleClifford Wolf2018-05-313-0/+152
* Add DelayInfo structClifford Wolf2018-05-291-2/+10
* Progress in chip.h APIClifford Wolf2018-05-262-32/+174
* Progress in ice40 chipdbClifford Wolf2018-05-264-52/+131
* Start work on iCE40 chipdbClifford Wolf2018-05-266-0/+423
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