Progress in ice40 chipdb

Signed-off-by: Clifford Wolf <clifford@clifford.at>

4 files changed, 131 insertions, 52 deletions

diff --git a/ice40/chip.cc b/ice40/chip.cc
index df7590ee..bca78a14 100644
--- a/ice40/chip.cc
+++ b/ice40/chip.cc
@@ -19,8 +19,17 @@
 
 #include "chip.h"
 
-Chip::Chip(ChipArgs)
+Chip::Chip(ChipArgs args)
 {
+	if (args.type == ChipArgs::LP384) {
+		num_bels = 0;
+		bel_data = nullptr;
+		num_wires = num_wires_384;
+		wire_data = wire_data_384;
+		return;
+	}
+
+	abort();
 }
 
 BelRange Chip::getBels() const
diff --git a/ice40/chip.h b/ice40/chip.h
index 7dd39b63..ed7f64b2 100644
--- a/ice40/chip.h
+++ b/ice40/chip.h
@@ -22,6 +22,48 @@
 #ifndef CHIP_H
 #define CHIP_H
 
+// -----------------------------------------------------------------------
+
+struct BelInfoPOD
+{
+	const char *name;
+};
+
+struct WireDelayPOD
+{
+	int32_t wire_index;
+	float delay;
+};
+
+struct BelPortPOD
+{
+	int32_t bel_index;
+	int port_index;
+};
+
+struct WireInfoPOD
+{
+	const char *name;
+	int num_uphill, num_downhill, num_bidir;
+	WireDelayPOD *wires_uphill, *wires_downhill, *wires_bidir;
+
+	int num_bels_downhill;
+	BelPortPOD bel_uphill;
+	BelPortPOD *bels_downhill;
+};
+
+extern int num_wires_384;
+extern int num_wires_1k;
+extern int num_wires_5k;
+extern int num_wires_8k;
+
+extern WireInfoPOD wire_data_384[];
+extern WireInfoPOD wire_data_1k[];
+extern WireInfoPOD wire_data_5k[];
+extern WireInfoPOD wire_data_8k[];
+
+// -----------------------------------------------------------------------
+
 struct BelId
 {
 	int32_t index = -1;
@@ -59,6 +101,8 @@ namespace std
 	};
 }
 
+// -----------------------------------------------------------------------
+
 struct BelIterator
 {
 	BelId *ptr = nullptr;
@@ -75,22 +119,31 @@ struct BelRange
 	BelIterator end() const { return e; }
 };
 
-struct WireIterator
+// -----------------------------------------------------------------------
+
+struct AllWiresIterator
 {
-	WireId *ptr = nullptr;
+	int cursor;
 
-	void operator++() { ptr++; }
-	bool operator!=(const WireIterator &other) const { return ptr != other.ptr; }
-	WireId operator*() const { return *ptr; }
+	void operator++() { cursor++; }
+	bool operator!=(const AllWiresIterator &other) const { return cursor != other.cursor; }
+
+	WireId operator*() const {
+		WireId ret;
+		ret.index = cursor;
+		return ret;
+	}
 };
 
-struct WireRange
+struct AllWiresRange
 {
-	WireIterator b, e;
-	WireIterator begin() const { return b; }
-	WireIterator end() const { return e; }
+	AllWiresIterator b, e;
+	AllWiresIterator begin() const { return b; }
+	AllWiresIterator end() const { return e; }
 };
 
+// -----------------------------------------------------------------------
+
 struct WireDelay
 {
 	WireId wire;
@@ -99,11 +152,17 @@ struct WireDelay
 
 struct WireDelayIterator
 {
-	WireDelay *ptr = nullptr;
+	WireDelayPOD *ptr = nullptr;
 
 	void operator++() { ptr++; }
 	bool operator!=(const WireDelayIterator &other) const { return ptr != other.ptr; }
-	WireDelay operator*() const { return *ptr; }
+
+	WireDelay operator*() const {
+		WireDelay ret;
+		ret.wire.index = ptr->wire_index;
+		ret.delay = ptr->delay;
+		return ret;
+	}
 };
 
 struct WireDelayRange
@@ -113,6 +172,8 @@ struct WireDelayRange
 	WireDelayIterator end() const { return e; }
 };
 
+// -----------------------------------------------------------------------
+
 struct BelPin
 {
 	BelId bel;
@@ -135,6 +196,8 @@ struct BelPinRange
 	BelPinIterator end() const { return e; }
 };
 
+// -----------------------------------------------------------------------
+
 struct GuiLine
 {
 	float x1, y1, x2, y2;
@@ -153,46 +216,18 @@ struct ChipArgs
 	} type = NONE;
 };
 
-struct BelInfo
-{
-	const char *name;
-};
-
-struct WireDelayPOD
-{
-	int32_t wire_index;
-	float delay;
-};
-
-struct BelPortPOD
-{
-	int32_t bel_index;
-	int port_index;
-};
-
-struct WireInfo
-{
-	const char *name;
-	int num_uphill, num_downhill, num_bidir;
-	WireDelayPOD *wires_uphill, *wires_downhill, *wires_bidir;
-
-	int num_bels_downhill;
-	BelPortPOD bel_uphill;
-	BelPortPOD *bels_downhill;
-};
-
 struct Chip
 {
 	int num_bels, num_wires;
-	BelInfo *bel_data;
-	WireInfo *wire_data;
+	BelInfoPOD *bel_data;
+	WireInfoPOD *wire_data;
 
 	// ...
 
 	Chip(ChipArgs args);
 
-	void setBelActive(BelId bel, bool active);
-	bool getBelActive(BelId bel);
+	void setBelActive(BelId, bool) { }
+	bool getBelActive(BelId) { return true; }
 
 	BelId getBelByName(IdString name) const;
 	WireId getWireByName(IdString name) const;
@@ -208,11 +243,43 @@ struct Chip
 	vector<GuiLine> getBelGuiLines(BelId bel) const;
 	vector<GuiLine> getWireGuiLines(WireId wire) const;
 
-	WireRange getWires() const;
-	WireDelayRange getWiresUphill(WireId wire) const;
-	WireDelayRange getWiresDownhill(WireId wire) const;
-	WireDelayRange getWiresBidir(WireId wire) const;
-	WireDelayRange getWireAliases(WireId wire) const;
+	AllWiresRange getWires() const
+	{
+		AllWiresRange range;
+		range.b.cursor = 0;
+		range.e.cursor = num_wires;
+		return range;
+	}
+
+	WireDelayRange getWiresUphill(WireId wire) const
+	{
+		WireDelayRange range;
+		range.b.ptr = wire_data[wire.index].wires_uphill;
+		range.e.ptr = wire_data[wire.index].wires_uphill + wire_data[wire.index].num_uphill;
+		return range;
+	}
+
+	WireDelayRange getWiresDownhill(WireId wire) const
+	{
+		WireDelayRange range;
+		range.b.ptr = wire_data[wire.index].wires_downhill;
+		range.e.ptr = wire_data[wire.index].wires_downhill + wire_data[wire.index].num_downhill;
+		return range;
+	}
+
+	WireDelayRange getWiresBidir(WireId wire) const
+	{
+		WireDelayRange range;
+		range.b.ptr = wire_data[wire.index].wires_bidir;
+		range.e.ptr = wire_data[wire.index].wires_bidir + wire_data[wire.index].num_bidir;
+		return range;
+	}
+
+	WireDelayRange getWireAliases(WireId wire) const
+	{
+		WireDelayRange range;
+		return range;
+	}
 
 	// the following will only operate on / return "active" BELs
 	// multiple active uphill BELs for a wire will cause a runtime error
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index eec7aad0..9e783dd0 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -108,7 +108,7 @@ for wire in range(num_wires):
 
     wireinfo.append(info)
 
-print("extern WireInfo wire_data_%s[%d];" % (dev_name, num_wires))
-print("WireInfo wire_data_%s[%d] = {" % (dev_name, num_wires))
+print("int num_wires_%s = %d;" % (dev_name, num_wires))
+print("WireInfoPOD wire_data_%s[%d] = {" % (dev_name, num_wires))
 print(",\n".join(wireinfo))
 print("};")
diff --git a/ice40/main.cc b/ice40/main.cc
index e3a784ca..1a63f003 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -21,7 +21,10 @@
 
 int main()
 {
-	Design design(ChipArgs{});
+	ChipArgs chipArgs;
+	chipArgs.type = ChipArgs::LP384;
+
+	Design design(chipArgs);
 
 	for (auto bel : design.chip.getBels())
 		printf("%s\n", design.chip.getBelName(bel).c_str());